Custom Processor Design with Verification: Insights from Codasip at DAC

Custom Processor Design with Verification: Insights from Codasip at DAC
by Admin on 08-01-2024 at 3:00 pm

At the 62nd Design Automation Conference (DAC) on July 22, 2024, Philip Bena from Codasip delivered a compelling session on processor customization, emphasizing a responsible approach that prioritizes verification. Codasip, a European company with a global presence, offers a unique combination of RISC-V processor IP and… Read More


Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks

Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks
by Daniel Nenni on 05-10-2024 at 8:00 am

EW Award 24 Logo winner safety Security coloured RGB 300dpi 960x117

Most organizations are aware of cybercrime attempts such as phishing, installing malware from dodgy websites or ransomware attacks and undertake countermeasures. However, relatively little attention has been given to memory safety vulnerabilities such as buffer overflows or over-reads. For decades, the industry has created… Read More


Re-configuring RISC-V Post-Silicon

Re-configuring RISC-V Post-Silicon
by Bernard Murphy on 12-07-2022 at 6:00 am

Post Silicon RISC V extensions min

How do you reconfigure system characteristics? The answer to that question is well established – through software. Make the underlying hardware general enough and use platform software to update behaviors and tweak hardware configuration registers. This simple fact drove the explosion of embedded processors everywhere … Read More