Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure

Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure
by Kalar Rajendiran on 12-19-2023 at 6:00 am

Alphawave Semi 224G SerDes 1st TestChip

In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More


Successful 3DIC design requires an integrated approach

Successful 3DIC design requires an integrated approach
by Kalar Rajendiran on 11-13-2023 at 6:00 am

Siemens EDA 3DIC Graphics

While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal… Read More


Podcast EP193: A Look at the Engineering Tracks for DAC 2024 with Frank Schirrmeister

Podcast EP193: A Look at the Engineering Tracks for DAC 2024 with Frank Schirrmeister
by Daniel Nenni on 11-10-2023 at 10:00 am

Dan is joined by Frank Schirrmeister. Frank is vice president of solutions and business development at Arteris. He leads activities for industry verticals, including automotive and enterprise computing and technology horizontals like artificial intelligence, machine learning, and safety. For DAC 2024, Frank is the vice… Read More


Arm Total Design Hints at Accelerating Multi-Die Activity

Arm Total Design Hints at Accelerating Multi-Die Activity
by Bernard Murphy on 11-02-2023 at 6:00 am

multi die

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems… Read More


Managing IP, Chiplets, and Design Data

Managing IP, Chiplets, and Design Data
by Daniel Payne on 10-23-2023 at 10:00 am

Managing IP min

Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked… Read More


The Path to Chiplet Architecture

The Path to Chiplet Architecture
by Paul McLellan on 10-19-2023 at 10:00 am

The Path to Chiplet Architecture

If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.

When 3D packaging was first introduced, there were not really any effective… Read More


Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design

Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design
by Kalar Rajendiran on 10-10-2023 at 6:00 am

AresCORE UCIe PHY Support for All Package Types

The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs,… Read More


Keysight EDA 2024 Delivers Shift Left for Chiplet and PDK Workflows

Keysight EDA 2024 Delivers Shift Left for Chiplet and PDK Workflows
by Don Dingee on 09-28-2023 at 8:00 am

Chiplet PHY Designer

Much of the recent Keysight EDA 2024 announcement focuses on high-speed digital (HSD) and RF EDA features for Advanced Design System (ADS) and SystemVue users, including RF System Explorer, DPD Explorer (for digital pre-distortion), and design elements for 5G NTN, DVB-S2X, and satcom phased array applications. Two important… Read More


Podcast EP179: An Expert Panel Discussion on the Move to Chiplets

Podcast EP179: An Expert Panel Discussion on the Move to Chiplets
by Daniel Nenni on 09-01-2023 at 10:00 am

Dan is joined by a panel of experts to discuss chiplets and 2.5/3D design. The panelists are: Saif Alam – Vice President of Engineering at Movellus Inc., Tony Mastroianni Siemens EDA- Advanced Packaging Solutions Director and Craig Bishop – CTO Deca Technologies.

In this spirited and informative discussion the … Read More


WEBINAR: The Power of Formal Verification: From flops to billion-gate designs

WEBINAR: The Power of Formal Verification: From flops to billion-gate designs
by Daniel Nenni on 08-15-2023 at 5:00 pm

cover img new 400X400

Semiconductor industry is going through an unprecedented technological revolution with AI/ML, GPU, RISC-V, chiplets, automotive and 5G driving the hardware design innovation. The race to deliver high performance, optimizing power and area (PPA), while ensuring safety and security is truly on. It has never been a more excitingRead More