Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award
by Daniel Nenni on 10-06-2025 at 10:00 am

TSMC 3D Fabric Packaging TSMC OIP 2025

In a significant milestone for the semiconductor industry, Teradyne was honored as the 2025 TSMC Open Innovation Platform® Partner of the Year for TSMC 3DFabric® Testing. This award, announced on September 25, 2025, underscores the deep collaboration between Teradyne, a leader in automated test equipment and robotics, and… Read More


Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation
by Daniel Nenni on 10-01-2025 at 10:00 am

UNDER EMBARGO 1PM PT Sept 24 Synopsys TSMC OIP 2025 (1)

In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages … Read More


Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions

Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions
by Daniel Nenni on 09-29-2025 at 6:00 am

synopsys tsmc oip 2025 leading the next wave of ai and multi die innovation for tsmc advanced node designs

Synopsys has deepened its collaboration with TSMC certifying the Ansys portfolio of simulation and analysis tools for TSMC’s cutting-edge manufacturing processes including N3C, N3P, N2P, and A16. This partnership empowers chip designers to perform precise final checks on designs, targeting applications in AI acceleration,… Read More


EDA Tool Support for GAA Process Designs

EDA Tool Support for GAA Process Designs
by Daniel Nenni on 11-23-2020 at 6:00 am

GAA FinFET

With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device.  The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet.

I will talk… Read More


ANSYS Electronics Simulation Expo – A View from Industry

ANSYS Electronics Simulation Expo – A View from Industry
by Pawan Fangaria on 10-24-2014 at 7:30 am

As we are seeing more and more automation in most of our activities, not only through software but also smart electronics (at cutting-edge technologies) equipped with processors, micro-controllers, sensors and so on which make a whole system as an integrated entity on a small piece of semiconductor intertwined with other systems… Read More


Smartphones in the BRICs

Smartphones in the BRICs
by Paul McLellan on 06-24-2011 at 2:45 pm

The latest edition of GSA Forum has an article by Aveek Sarkar of Apache on system design for emerging market needs. The BRIC (Brazil, Russia, India, China) type countries are characterized by a small rich segment, a large and growing middle class and a large poor segment. One big trend is that smart phone use is expanding very fast.… Read More