Reset Domain Crossing (RDC) Challenges

Reset Domain Crossing (RDC) Challenges
by Daniel Payne on 12-18-2024 at 10:00 am

Origin of reset trees

In the early days an IC had a single clock and a single reset signal, making it a simple matter to reset the chip into a known, stable state, so there was little need for detailed analysis. For modern designs there can be dozens to hundreds of clocks, creating separate domains and some use of asynchronous resets, so the challenge of ensuring… Read More


Elevating Your SoC for Reconfigurable Computing – EFLX® eFPGA and InferX™ DSP and AI

Elevating Your SoC for Reconfigurable Computing – EFLX® eFPGA and InferX™ DSP and AI
by Kalar Rajendiran on 05-28-2024 at 10:00 am

Use Case eFPGA Complementing Signal Processing

Field-Programmable Gate Arrays (FPGAs) have long been celebrated for their unmatched flexibility and programmability compared to Application-Specific Integrated Circuits (ASICs). And the introduction of Embedded FPGAs (eFPGAs) took these advantages to new heights. eFPGAs offer on-the-fly reconfiguration capabilities,… Read More


Low power techniques

Low power techniques
by Paul McLellan on 12-08-2011 at 5:49 pm

There was recently a forum discussion about the best low power techniques. Not surprisingly we didn’t come up with a new technique nobody had ever thought of but it was an interesting discussion.

First there are the techniques that by now have become standard. If anyone wants more details on these then two good resources are… Read More