Tag: architecture

Webinar: What it really takes to build a future-proof AI architecture?

Webinar: What it really takes to build a future-proof AI architecture?
by Admin on 06-26-2025 at 7:54 pm

Abstract

As AI workloads increasingly dominate numerous cloud and edge applications, building a scalable, efficient, and future-ready AI chips is no longer optional—it’s essential. This webinar explores the latest AI trends, highlighting the growing demand for intelligent processing closer to the data source and

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Architectural Planning of 3D IC

Architectural Planning of 3D IC
by Daniel Payne on 11-15-2022 at 10:00 am
Categories: Chiplet, EDA, Siemens EDA

3D IC min

Before chiplets arrived, it seemed like designing an electronic system was a bit simpler, as a system on chip (SoC) methodology was well understood, and each SoC was mounted inside a package, then the packages for each component were interconnected on a printed circuit board (PCB). The emerging trend to design a 3D IC using chiplets… Read More

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A 2021 Summary of OpenFive

A 2021 Summary of OpenFive
by Kalar Rajendiran on 02-01-2022 at 10:00 am
Categories: Chiplet, OpenFive, Semiconductor Services

Key Features of the Edge AI Vision Platform

Building a better mousetrap plays a key role in achieving market success in any industry. Of course, building one requires differentiating the product from the others already in the market. A differentiated product can even lead to creating demand for new products in adjacent markets. All of this is great but how do you implement… Read More

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Architecting an ML Design

Architecting an ML Design
by Bernard Murphy on 08-14-2018 at 7:00 am
Categories: AI, EDA, Synopsys

Discussion on machine learning (ML) and hardware design has been picking up significantly in two fascinating areas: how ML can advance hardware design methods and how hardware design methods can advance building ML systems. Here I’ll talk about the latter, particularly about architecting ML-enabled SoCs. This approach is … Read More

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System Level Formal

System Level Formal
by Bernard Murphy on 01-09-2018 at 7:00 am
Categories: EDA, Oski Technology
3 Comments

Two recently announced vulnerabilities in major processor platforms should remind us that bugs don’t organize themselves to appear only in domains we know how to test comprehensively. Both Meltdown and Spectre (the announced problems) are potential hardware system-level issues allowed by interactions between speculative… Read More

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The Practice of Low Power Design

The Practice of Low Power Design
by Bernard Murphy on 11-14-2017 at 7:00 am
Categories: Cadence, EDA
1 Comment

For any given design objective, there is what we in the design automation biz preach that design teams should do, and then there’s what designs teams actually do. For some domains, the gap between these two may be larger than others, but we more or less assume that methodologies which have been around for years and are considered to… Read More

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Virtual Modeling Drives Auto Systems TTM

Virtual Modeling Drives Auto Systems TTM
by Bernard Murphy on 03-27-2017 at 7:00 am
Categories: Automotive, EDA, Synopsys

The electronics market for automotive applications is distinguished by multiple factors. This is a very fast growing market – electronics now account for 40% of a car’s cost, up from 20% just 10 years ago. New technologies are gaining acceptance, for greener and safer operation and for a more satisfying consumer experience. Platforms… Read More

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Develop A Complete System Prototype Using Vista VP

Develop A Complete System Prototype Using Vista VP
by Pawan Fangaria on 09-22-2013 at 6:00 pm
Categories: EDA, Siemens EDA

Yes, it means complete hardware and software integration, debugging, verification, optimization of performance and power and all other operational aspects of an electronic system in semiconductor design. In modern SoCs, several IPs, RTL blocks, software modules, firmware and so on sit together on a single chip, hence making… Read More

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How to Design an LTE Modem

How to Design an LTE Modem
by Paul McLellan on 09-16-2013 at 4:24 pm
Categories: EDA, Synopsys

Designing an LTE modem is an interesting case study in architectural and system level design because it is pretty much on the limit of what is possible in a current process node such as 28nm. I talked to Johannes Stahl of Synopsys about how you would accomplish this with the Synopsys suite of system level tools. He is the first to admit… Read More

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Cavium Adopts JasperGold Architectural Modeling

Cavium Adopts JasperGold Architectural Modeling
by Paul McLellan on 03-05-2013 at 7:00 am
Categories: EDA

Cavium designs some very complex SoCs containing multiple ARM or MIPS cores at 32 and 64 bit. This complexity leads to major challenges in validating the overall chip architecture to ensure that their designs will meet the requirements of their customers once they are completed, with performance as high as 100Gbps.

Cavium have… Read More