High-Speed Equivalence Checking

High-Speed Equivalence Checking
by Bernard Murphy on 09-28-2017 at 7:00 am

Following on product introductions for simulation and prototyping, physical verification and implementation earlier in the year, Anirudh Devgan (Exec VP and GM at Cadence), the king of speed and parallelism has done it again, this time with logic equivalence checking (LEC). Cadence recently announced an advance to their well-known… Read More


TSMC OIP and the Insatiable Computing Trend!

TSMC OIP and the Insatiable Computing Trend!
by Daniel Nenni on 09-14-2017 at 12:00 am

This year’s OIP was much more lighthearted than I remember which is understandable. TSMC is executing flawlessly, delivering new process technology every year. Last year’s opening speaker, David Keller, used the phrase “Celebrate the way we collaborate” which served as the theme for the conference. This year David’s… Read More


The CDNLive Keynotes

The CDNLive Keynotes
by Bernard Murphy on 04-25-2017 at 7:00 am

I’m developing a taste for user-group meetings. In my (fairly) recently assumed role as a member of the media, I’m only allowed into the keynotes, but from what I have seen, vendors work hard to make these fresh and compelling each year through big-bang product updates and industry/academic leaders talking about their work in bleeding-edge… Read More


Top Ten Insights on the EDA and Semiconductor Industry

Top Ten Insights on the EDA and Semiconductor Industry
by Tom Dillinger on 02-11-2016 at 7:00 am

I recently had the opportunity to chat with Anirudh Devgan, senior vice president and general manager at Cadence, who leads the Digital and Signoff Group. We discussed recent product development initiatives at Cadence, and talked about future EDA and semiconductor market opportunities. His insights and comments were keen … Read More