Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs

Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
by Admin on 05-05-2026 at 1:14 am

Featured Speaker:

  • Victoria Kolesov, Principal Engineer, Intel

In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’

Read More

Webinar: Intel: Enabling and Evaluating Intel EMIB-T Bridging Design with Synopsys Tools

Webinar: Intel: Enabling and Evaluating Intel EMIB-T Bridging Design with Synopsys Tools
by Admin on 04-29-2026 at 12:31 am

In this webinar, Intel will present how EMIB-T (Embedded Multi-die Interconnect Bridge with TSVs) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share a production-oriented EMIB-T reference methodology built … Read More


2026 Outlook with Dave Hwang of Alchip

2026 Outlook with Dave Hwang of Alchip
by Daniel Nenni on 01-26-2026 at 8:00 am

Dave Huang (2)

Dr. Dave Hwang joined Alchip in 2021 as General Manager of Alchip’s North America Business Unit.  He also serves as Senior Vice President, Business Development.  Prior to join Alchip, Dave served as Vice President, Worldwide Sales and Marketing for Global Unichip and in a variety of management and technical roles at TSMC.

Tell
Read More

Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation

Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation
by Daniel Nenni on 09-04-2025 at 10:00 am

Alchip 3D IC Test Chip TSMC N2

Today Alchip Technologies, a Taipei-based leader in high-performance and AI computing ASICs, announced a significant milestone with the successful tape-out of its 3D IC test chip. This achievement not only validates Alchip’s advanced 3D IC ecosystem but also positions the company as a frontrunner in the rapidly evolving field… Read More


Podcast EP305: On Overview of imec’s XTCO Program with Dr. Julien Ryckaert

Podcast EP305: On Overview of imec’s XTCO Program with Dr. Julien Ryckaert
by Daniel Nenni on 08-29-2025 at 10:00 am

Dan is joined by Dr. Julien Ryckaert who joined imec as a mixed-signal designer in 2000, specializing in RF transceivers, ultra-low power circuit techniques, and analog-to-digital converters. In 2010, he joined imec’s process technology division in charge of design enablement for 3DIC technology. Since 2013, he oversees… Read More


Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA

Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA
by Daniel Nenni on 06-20-2025 at 8:00 am

Dan is joined by Dr. John Ferguson, Director of Product Management for the Calibre nmDRC and 3DIC related products for Siemens EDA. John has worked extensively in the area of physical design verification. Holding several patents, he is also a frequent author in the physical design and verification domain. Current activities … Read More


Arteris Expands Their Multi-Die Support

Arteris Expands Their Multi-Die Support
by Bernard Murphy on 06-18-2025 at 6:00 am

multi die use cases min

I am tracking the shift to multi-die design, so it’s good to see Arteris extend their NoC expertise, connecting chiplets across an interposer. After all, network connectivity needs don’t stop at the boundaries of chiplets. A multi-die package is at a logical level just a scaled-up SoC for which you still need traffic routing and… Read More


Alchip’s Technology and Global Talent Strategy Deliver Record Growth

Alchip’s Technology and Global Talent Strategy Deliver Record Growth
by Kalar Rajendiran on 05-20-2025 at 10:00 am

Alchip TSMC 2nm N2

Alchip Technologies Ltd., a global leader in high-performance computing (HPC) and artificial intelligence (AI) ASIC design and production services, continues its trajectory of rapid growth and technical leadership by pushing the boundaries of advanced-node silicon, expanding its global design capabilities, and building… Read More


Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli

Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli
by Daniel Nenni on 05-09-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is once again joined by Anna Fontanelli, founder and CEO of MZ Technologies. In this discussion, more details of the challenges presented by advanced packaging and multi-die design are explored. Anna provides details of what’s involved in architectural … Read More


Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures

Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures
by Kalar Rajendiran on 02-12-2025 at 6:00 am

Chiplets A New Abstraction Layer

The semiconductor industry is facing a paradigm shift. Traditional scaling, once driven by Moore’s Law, is slowing down. For years, moving to smaller process nodes led to lower transistor costs and better performance. However, scaling from node to node now offers fewer benefits as wafer costs rise much more than the historical… Read More