Tag: 3dic

Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA

Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA
by Daniel Nenni on 06-20-2025 at 8:00 am
Categories: 3D IC, EDA, Events, Siemens EDA

Dan is joined by Dr. John Ferguson, Director of Product Management for the Calibre nmDRC and 3DIC related products for Siemens EDA. John has worked extensively in the area of physical design verification. Holding several patents, he is also a frequent author in the physical design and verification domain. Current activities … Read More

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Arteris Expands Their Multi-Die Support

Arteris Expands Their Multi-Die Support
by Bernard Murphy on 06-18-2025 at 6:00 am
Categories: 3D IC, AI, Arteris, IP

multi die use cases min

I am tracking the shift to multi-die design, so it’s good to see Arteris extend their NoC expertise, connecting chiplets across an interposer. After all, network connectivity needs don’t stop at the boundaries of chiplets. A multi-die package is at a logical level just a scaled-up SoC for which you still need traffic routing and… Read More

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Alchip’s Technology and Global Talent Strategy Deliver Record Growth

Alchip’s Technology and Global Talent Strategy Deliver Record Growth
by Kalar Rajendiran on 05-20-2025 at 10:00 am
Categories: 3D IC, AI, Alchip, Chiplet, FinFET, GAA, IP, Semiconductor Services, TSMC
1 Comment

Alchip TSMC 2nm N2

Alchip Technologies Ltd., a global leader in high-performance computing (HPC) and artificial intelligence (AI) ASIC design and production services, continues its trajectory of rapid growth and technical leadership by pushing the boundaries of advanced-node silicon, expanding its global design capabilities, and building… Read More

Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli

Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli
by Daniel Nenni on 05-09-2025 at 10:00 am
Categories: EDA, MZ Technologies

In this episode of the Semiconductor Insiders video series, Dan is once again joined by Anna Fontanelli, founder and CEO of MZ Technologies. In this discussion, more details of the challenges presented by advanced packaging and multi-die design are explored. Anna provides details of what’s involved in architectural … Read More

Webinar: Intel Presents: Modern EDA Solutions for Scalable Heterogeneous Systems

Webinar: Intel Presents: Modern EDA Solutions for Scalable Heterogeneous Systems
by Admin on 05-01-2025 at 3:18 pm

Featured Speakers:

  • Vivek Rajan, Sr. Principal Engineer, Intel
  • Amlendu Choubey, Sr. Director, Product Management, Synopsys

Why You Should Attend:

Rapidly emerging new workloads and disruptive architectures have highlighted the importance of advanced packaging and 3DIC technologies. The scaling of Moore’s Law has pushed… Read More

Webinar: AMD Presents: 3D Odyssey – Navigating the Depths of 3DIC Feasibility Analysis

Webinar: AMD Presents: 3D Odyssey – Navigating the Depths of 3DIC Feasibility Analysis
by Admin on 04-28-2025 at 12:44 pm

Date: May 21, 2025 | 10:00 AM PDT

Featured Speakers:

  • Nitin Navale, Principal Member of Technical Staff, AMD
  • Amlendu Choubey, Sr. Director, Product Management, Synopsys

Why You Should Attend:

With the rising demand for highly efficient 3DIC design and performance, it’s crucial to understand the IR and thermal landscape of a

… Read More
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Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures

Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures
by Kalar Rajendiran on 02-12-2025 at 6:00 am
Categories: 3D IC, Automotive, Cadence, Chiplet, EDA, IP

Chiplets A New Abstraction Layer

The semiconductor industry is facing a paradigm shift. Traditional scaling, once driven by Moore’s Law, is slowing down. For years, moving to smaller process nodes led to lower transistor costs and better performance. However, scaling from node to node now offers fewer benefits as wafer costs rise much more than the historical… Read More

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Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management

Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management
by Kalar Rajendiran on 02-11-2025 at 6:00 am
Categories: 3D IC, Chiplet, EDA, Keysight EDA

Voltage Transfer Function Crrosstalk Limit

Keysight, with deep roots tracing back to Hewlett-Packard, has long been at the forefront of innovation in electronic design and testing. It manufactures electronics test and measurement equipment and software. The company also owns its own foundry and makes custom chips and packages for its instrumentation business. Many… Read More

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Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?

Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
by Kalar Rajendiran on 01-28-2025 at 6:00 am
Categories: 3D IC, Chiplet, EDA, IP, Synopsys
2 Comments

Synopsys Predictions for Multi Die Designs in 2025

Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More

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Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters

Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
by Daniel Nenni on 11-06-2024 at 10:00 am
Categories: 3D IC, Ansys, Inc., EDA, Events, Synopsys

banner for webinar

The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More