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Mind The Gap – Boarding the Silicon Photonics Packaging Train

Mind The Gap – Boarding the Silicon Photonics Packaging Train
by Mitch Heins on 05-01-2016 at 8:00 pm

I’ve been doing a lot of reading on silicon photonics lately and I’ve come to realize that while there is much written on the development of individual silicon photonic components and devices (modulators, photo detectors, optical amplifiers and such) that much of the cost and therefore chances of economic success of integrated photonics solutions resides not in the silicon but in packaging of these solutions. Before the photonics platform can be used photonic ICs (PICs) must be integrated to their electrical IC (EIC) counterparts and the rest of the system.

One of the biggest challenges of this integration is getting light on and off the PIC from optical fiber. For integrated  photonics this is typically done either through edge couplers or grating couplers as shown in figure 1. The tricky (and costly) part comes in ‘minding the gap’ between the relatively large optical mode of fiber to the very small optical mode of a SOI on-chip wave-guide. To put this into perspective, the diameter of a single-mode lensed telecom fiber for 1550nm light is ~3um. This must be matched up to a SOI-waveguide mode with dimensions of ~ 220nm x 450nm. That’s an area difference of almost 2 orders of magnitude (~7 million nm[SUP]2[/SUP] vs 99,000 nm[SUP]2[/SUP]). More challenging is that SOI wave-guides typically only support TE-polarized modes of light an
d the light coming in from a fiber is usually unknown and unstable requiring a mode convertor to clean up the signal before entering the waveguide. The 1db alignment tolerance for a typical edge-coupler is sub-micron (~ +/- 500nm) requiring time consuming and expensive active alignment during packaging. Additionally, these couplers usually require laser-welding to secure the lensed-fiber to the PIC as epoxy bonding suffers from small alignment drifts that would not be tolerable at these dimensions. With laser-welding comes the need for more expensive packages to mitigate thermal expansion on the optical alignment. Peter O’Brien and the packaging group from Tyndall National Institute in Cork, Ireland do a great job of explaining all of the nuances of this and more in chapter 7 of the book, Silicon Photonics III. The end result being that while edge couplers are the standard for the packaging of III-V laser devices and do a good job reducing insertion loss and giving more broadband coupling, they add a substantially increased packaging cost for integrated PICs due to their stringent alignment requirements.

 The alternative to edge couplers are grating couplers that use diffraction gratings to couple a near incident fiber-mode to the wave-guide mode (figure 2). They are typically designed as a 10um x 10um periodic array of trenches, partially etched into the silicon layer. The trenches are usually curved to focus the light to the SOI-waveguide reducing the need for long space-consuming taper structures and can be designed to do double duty by taking care of the required polarization cleanup. The 1db alignment tolerance for these couplers are ~ +/- 2.5um. While still challenging, the process of “minding the gap” here is greatly simplified and much less costly compared to edge couplers. Grating couplers have the added benefit that they are fully CMOS flow compatible and allow for wafer-scale optical access at any point on the PIC surface enabling inline testing and characterization of the PIC before dicing.

 The biggest issue with grating couplers is their relatively high insertion loss. A standard grating coupler in 220nm SOI is -3db which equates to a 50% reduction in the transmitted power. In MPW runs from imec and CEA-Leti, users have experienced insertion losses as high as -5db. Several research groups are working on this and have reported devices in the labs using bottom-reflectors that have insertion loss down to -1db but these devices have not yet seen production. The other major concern for grating couplers is the need for near incident light making for bulky and delicate vertical connections from fiber to the PIC. To “mind this gap”, a quasi-planar approach (figure 7.4) has been developed in which the fiber lies flat on the surface of the PIC with a 40[SUP]0[/SUP] polished facet that directs the fiber-mode onto the grating coupler at the correct angle. Due to their relaxed alignment constraints these connections can be made with less expensive epoxy bonding. This is especially helpful for fiber-array connections that have multiple fiber-channels in the same connector where you can amortize the cost to connect multiple channels across one alignment task. As an added bonus, grating couplers can also be used with VCSELs (vertical cavity surface-emitting lasers) that are directly flip-chipped and bonded over the PIC couplers.

In the end, the best fiber-coupling solutions for a given PIC is strongly application and cost-dependent, but no matter what you do, to make your PIC design successful you’ll need to “mind the packaging gap” while boarding your silicon photonics train.


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