5 Talks on RISC-V

Veriest recently hosted a webinar focusing on RISC-V as a forerunner of ongoing open-source revolution in chip design. Speakers were distinguished professionals from industry and academia. Webinar covered topics from market trends to open-source hardware initiatives, tools and methodologies.

Zvonimir Bandić: RISC-V market update and CHIPS Alliance

Zvonimir is a Research Staff Member and Senior Director of Next Generation Platform Technologies Department at Western Digital (WD) and Chairman at CHIPS Alliance. He shared a story of how RISC-V came to WD accidentally from Berkeley University and made a huge impact on the company. Zvonimir cited a report from 2020. that claims that 23% percent of all ASIC and FPGA projects incorporate RISC-V in some way, while his personal feeling is that this percentage is even higher. Some of the markets where RISC-V already found its place are Data Centers, Cloud, HPC, Telecom, Automotive, Consumer and IoT, AI/ML, Edge computing etc. It is estimated that RISC-V CPU core market will grow at 114.9% CAGR, capturing over 14% of all CPU cores by 2025 – nearly 80 billion cores. Zvonimir claims that the core is only 3% of the whole ecosystem and that along with the core market, the surrounding IP and software markets will grow as well, offering a vast number of opportunities for companies and individuals to jump on-board.

Some of the main challenges in chip design today are development cost, time-to-market and need for purpose-built architecture. CHIPS Alliance is an organization looking to address these challenges by focusing on open-source hardware and open-source software for hardware design. It develops and hosts open-source RISC-V CPUs, hardware IPs and open-source ASIC & FPGA development tools. People and organizations looking to start design of their own product can find everything they need on CHIPS Alliance GitHub.

Prof. Borivoje Nikolić: Chipyard – Generating the next wave of custom silicon

Prof. Nikolić is a Distinguished Professor of Engineering at University of California, Berkeley. He shared insights on how RISC-V was born at Berkeley and how they are addressing main challenges in the chip design these days. Like Zvonimir, prof. Nikolić sees increased market demand for specialized chips and main challenges are in development cost and time it takes to build custom chip. At Berkeley they believe that current way of delivering IPs as black boxes greatly affect reusability. Instead of delivering instances, their approach is to use parametrized generators to describe the hardware and generate RTL. Generators are written in a hardware design language Chisel which is based on Scala. Generators not only provide easy way to customize designs, but also enable agile hardware development and fast turn-around cycles, something that is hard to achieve with traditional approach. Proof of this concept is Rocket Chip, a parametrized SoC generator with hundreds of commercial implementations.

To build a complete chip, a lot of open—source components are used. To connect tooling, generators and flows together, at Berkely they created a framework called Chipyard which is a one-stop-shop for SoC agile design.

Vladislav Palfy: OneSpin 360 processor verification app

Vladislav is a Senior Applications Engineering Manager at OneSpin. OneSpin company is a part of Siemens EDA and member of RISC-V International and Open Hardware Group. Vladislav explained how OneSpin 360 product can be used to execute formal verification of RISC-V core. Also, Vladislav pointed out the advantages of formal verification over simulation and why it is especially suitable for such complex design as a processor. In functional simulation it is very hard if not impossible to describe and cover all states. In OneSpin 360, the formal verification test process is automated, no test development nor assertion specification is required, and runtime and coverage closure are much faster. In addition, formal verification will help us find bugs we were not looking for, but also discover if there are functionalities which are not documented – this case is something they had with one of the popular RISC-V cores. OneSpin 360 supports RISC-V extensions, custom instructions as well as RISC-V cores specified in Chisel. In case of an issue, tool offers graphical environment for debugging where user can see failing checker, trace and code that caused the failure.

Siniša Stanojlović: RISC-V Memory protection

Siniša is a CEO of company Micro Circuits Development, a professional services provider for embedded systems. Siniša elaborated on vulnerabilities of all-connected/all-smart devices. RISC-V based devices are not immune to these threats, but they are different. While RISC-V devices implement similar security modules as other architectures, key difference is that they are open. Like in software, some see this openness as an advantage, others as a disadvantage.

Further Siniša focused on the example of memory protection in RISC-V through memory isolation. To achieve this, RISC-V ISA includes privileged instruction set specification which defines 3 types of computer systems:

• Systems that have only machine mode
• Systems with machine mode and user-mode.
• Systems with machine-mode, supervisor mode, and user-modes.

RISC-V has physical memory protection, which is used to enforce memory access restrictions on less privileged modes e.g. from machine mode RISC-V can configure which user mode applications can access to which parts of the memory.

Miloš Tomić: Getting started with open-source RISC-V cores

I’m an ASIC Design Engineer at Veriest, an ASIC design and verification services provider. RISC-V surge created a lot of new business opportunities for service companies in the semiconductor industry.

For this webinar, I shared my view on RISC-V ecosystem, and my RISC-V enrolling experience. The focus was on available open-source core implementations and their specifics. I covered some of the key consideration that had to be made when choosing an open-source core for a new project. This includes core features, target application and technology, software requirements, licensing etc.

In the end, a short summary and comparison of some of the most widespread RISC-V implementation was given:

• Ibex, CV32E40P, CVA6
• SweRV
• Rocket Chip, BOOM

Finally, conclusion was that you can build your own RISC-V SoC just by using open-source tools and components, and there is more than one path you can take.
We’re looking forward to continuing to explore this interesting topic in future events. If would like to be informed about such event, please let us know here.

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