Power densities on chips increased from 50-100 W/cm2 in 2010 to 200 W/cm2 in 2020, creating a significant challenge in removing and spreading heat to ensure reliable chip operation. The DAC 2025 panel discussion on new cooling strategies for future computing featured experts from NVIDIA Research, Cadence, ESL/EPFL, the University… Read More
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Arteris at the 2025 Design Automation Conference #62DAC
Key Takeaways:
- Expanded Multi-Die Solution: Arteris showcases its foundational technology for rapid chiplet-based innovation. Check out the multi-die highlights video.
- Ecosystem compatibility: Supported through integration with products from major EDA and foundry partners, including Cadence, Synopsys, and global
Secure-IC at the 2025 Design Automation Conference #62DAC
Secure-IC at DAC 2025: Building Trust into Tomorrow’s Chips and Systems
As semiconductor innovation accelerates, the chiplet-based design paradigm is redefining the landscape of advanced electronic systems. At DAC 2025, Secure-IC (booth #1208) will present a comprehensive suite of technologies engineered to address the… Read More
Mixel at the 2025 Design Automation Conference #62DAC
Mixel, Inc., a leading provider of mixed-signal interface IP, will exhibit at booth #2616 at Design Automation Conference (DAC) 2025 on June 23-25. The company will demonstrate its latest customer demos featuring Mixel’s MIPI PHY IP and LVDS IP. Mixel’s customers include many of the world’s largest semiconductors and system… Read More
Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond
As the computing industry seeks more flexible, scalable, and open hardware architectures, RISC-V has emerged as a compelling alternative to proprietary instruction set architectures. At the forefront of this revolution stands Andes Technology, offering a comprehensive lineup of RISC-V processor solutions that go far beyond… Read More
Andes Technology: A RISC-V Powerhouse Driving Innovation in CPU IP
As it celebrates its 20th anniversary in 2025, Andes Technology stands as a defining force in the RISC-V movement—an open computing revolution. What began in 2005 as a bold vision to deliver high-efficiency Reduced Instruction Set Computing (RISC) processor IP has evolved into a company whose innovations power billions of devices… Read More
Automotive Functional Safety (FuSa) Challenges
Modern vehicles have become quite sophisticated, like a supercomputer on wheels. They integrate a vast number of electronic components, including thousands of chips, to deliver advanced functionalities ranging from infotainment to critical safety systems. This increasing complexity necessitates a robust approach to … Read More
The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
In an era defined by complex chip architectures, ever-shrinking technology nodes and very demanding applications, Silicon Lifecycle Management (SLM) has become a foundational strategy for optimizing performance, reliability, and efficiency across the lifespan of a semiconductor device. Central to effective SLM are Process,… Read More
Andes RISC-V CON in Silicon Valley Overview
RISC-V conferences have been at full capacity and I expect this one will be well attended as well. Andes is the biggest name in RSIC-V. The most notable thing about RISC-V conferences is the content. Not only is the content deep, it is international from the top companies in the industry. It is hard to find a design win these days without… Read More
Predictive Load Handling: Solving a Quiet Bottleneck in Modern DSPs
When people talk about bottlenecks in digital signal processors (DSPs), they usually focus on compute throughput: how many MACs per second, how wide the vector unit is, how fast the clock runs. But ask any embedded AI engineer working on always-on voice, radar, or low-power vision—and they’ll tell you the truth: memory stalls … Read More








Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs