Bug Hunting in NoCs. Innovation in VerificationDespite NoCs being finely tuned in legacy subsystems,…Read More
Alphawave Semi Unlocks 1.2 TBps Connectivity for HPC and AI Infrastructure with 9.2 Gbps HBM3E SubsystemIn the rapidly evolving fields of high-performance computing…Read More
Elevate Your Analog Layout Design to New HeightsAnalog IC layout is a demanding endeavor as…Read More
Analog Bits Momentum and a Look to the FutureAnalog Bits is aggressively moving to advanced nodes.…Read More
Spatial audio concepts targeted for earbuds and soundbarsSpatial audio technologies deliver more realistic sound by…Read More
Hello Daniel,
I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER… Read More
Back in the 2008 financial Crises, GM was finally brought to its knees and had to face a radical makeover. They asked for a bailout from the government that allowed the unions to swap out lower compensation for equity, something no union would do unless the alternative was to shutter the doors. The bondholders and the shareholders… Read More
Wow! We always hear semiconductor companies complain about the lack of innovation amongst the EDA leaders. Placing high on the Deloitte 500 list shows that innovation is alive and well in EDA and it IS possible to have a meaningful impact regardless of your overall size. It is worth noting that there are very few EDA companies that… Read More
Lunch with Jim Lai, President of Global Unichip(GUC), was the highlight of my week, I had a very nice crab cake salad. As you may have read, GUC announced itself as the “Flexible ASIC Leader” taking direct aim at the traditional ASIC market led by the likes of IBM, ST Micro, TI, Renesas, and Samsung. This will be like “shooting fish in… Read More
ISTFA
Silicon Valley is a great location for trade shows and technical conferences, so if you have an interest in test and failure analysis then don’t miss out on the 37th annual International Symposium for Testing and Failure Analysis. This year ISTFA will be held from Sunday, November 13th thru Thursday, November 17th … Read More
The “old saw” is “To Sell in May and Go Away.” It’s a Maxim that particularly applies to semiconductor stocks as they typically drop from a post April earnings peak through the summer doldrums to a late September nadir only to be revived in the prelude of October earnings. It has happened again this year, although the path taken by the… Read More
Wally Rhines’s keynote at the ARM TechCon was about differentiation and how to use it to create measurable value. We all know what differentiation means in some intuitive sense, but how do you make it measurable? Wally’s answer was that differentiation is a measure of the difficulty of switching suppliers and is best… Read More
Every analog designer needs a foundry PDK (Process Design Kits) and EDA tools to design, layout and verify their AMS chip or IP. This week I had a chance to conduct an email interview with Taek-Soo Kim, VP of Technical Engineering at Dongbu HiTek in Korea. This specialty foundry supplies analog silicon worldwide.
Interview
Q: Tell… Read More
Introduction from Hezi Saar: Eric’s latest viewpoints and reports are host onIPnestas well as on Semiwikiand you can find information related to various Interface IP: USB 3.0, PCIe, SATA, DDRn, MIPI, HDMI and more.
Q: Eric, give us a quick introduction about your background as it relates to interface IP
A: I have spent 20 years working… Read More
By Carey Robertson, Director of Product Marketing, Mentor Graphics
IC physical verification requires a number of different types of checking, the most familiar being design rule checking (DRC), layout vs. schematic (LVS) checking, and parasitic extraction combined with circuit simulation. Fundamentally, it does not matter… Read More
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Intel’s Death Spiral Took Another Turn