If your next SoC uses an ARM Cortex-A9 and has an industrial application, then you can save much design and debug time by using a prototyping platform. The price to prototype is quite affordable, and the methodology has a short learning curve. Bill Tomasan Aldec Research Engineer conducted a webinar today on: ARM Cortex SoC Prototyping… Read More




Synopsys ♥ TSMC!
Dr. Paul McLellan and I will be covering the Silicon Valley SNUG live again this year. Unfortunately we are only allowed to see the keynotes (same thing with CDNLive) but they look very good:
Keynote Address: Massive Innovation and Collaboration into the “GigaScale” Age!
Aart de Geus, Chairman and co-CEO, Synopsys,… Read More
Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!
Those who have read the numerous articles I have written about MIPI, or PCIe, or the fusion of both named “Mobile Express” know my position: the question is not “Will Mobile devices support PCI Express?” but “When will we see Mobile devices integrating Mobile Express?” I was not really surprised by the Press Release that Cadence … Read More
Formal Verification of Power Intent
I can’t imagine that any SoC today is designed without taking intense interest in how much power the chip will consume, whether it is destined for a mobile phone or tethered in a cloud datacenter. One challenge with power is that adding features like voltage islands or power-down areas require changes to the netlist such as… Read More
Margaret Butler: One Woman’s Life in Science
46 years in Computing, 1945-1991
Margaret (Kampschaefer) Butler was a pioneer in technology, a ground-breaking woman who graduated with a B.S in Mathematics and Statistics in 1944, and followed a fascinating career path in the public sector starting in the earliest days of computers and nuclear energy. One of the early female… Read More
Standard Cell Library Characterization
Standard cell library characterization has been around for decades, Synopsys has been offering Liberty NCXand Cadence has Virtuoso Foundation IP Characterization. What’s new is that Mentor Graphics acquired the Z Circuit technology for library characterization and has integrated it with the Eldo Classic circuit … Read More
Ensuring timing of Custom Designs with large embedded memories – A big burden has solution!
In 1990s when designs were small, I was seeing design and EDA community struggling to improve upon huge time taken to verify the circuits, specifically with Spice and the like. I was myself working on developing tool for transistor level static timing analysis (STA) mainly to gain on time (eliminating the need of exhaustive set … Read More
EDPS Monterey. Agenda Now Available
For 20 years there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey at the Monterey Beach Resort. This year it is Thursday and Friday April 18th/19th.
The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC —… Read More
RTDA at Altera
I talked to Yaron Kretchmer of Altera to find out how they are using RTDA’s products. I believe that Altera are the oldest customer of RTDA, dating back over 15 years, originally used by the operations team around the test floor before propagating out in the EDA and software worlds more recently.
Altera use two RTDA tools, LicenceMonitor… Read More
Samsung and the New World Order!
The keynotes at CDNLive today were very interesting, but rather than cover the slides and bullet points let me share with you my personal view of Samsung and how they are changing the semiconductor industry. Before I continue remember I’m just a blogger who shares observations, experiences, and opinions. This blog is for entertainment… Read More
Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI