Primarius 2B

Pairing RISC-V cores with NoCs ties SoC protocols together

Pairing RISC-V cores with NoCs ties SoC protocols together
by Don Dingee on 10-05-2023 at 6:00 am

An architecture pairing RISC-V cores with NoCs

Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting… Read More


The Quest for Bugs: “Verification is a Data Problem!”

The Quest for Bugs: “Verification is a Data Problem!”
by Bryan Dickman on 10-04-2023 at 10:00 am

The Quest for Bugs Verification is a data problem

Verification Data Analytics

Hardware Verification is a highly data-intensive or data-heavy problem. Verification Engineers recognise this and spend much of their time dealing with large and complex datasets arising from verification processes.

In “The Dilemmas of Hardware Verification” we explored the key challenges … Read More


Samtec Increases Signal Density Again with Analog Over Array™

Samtec Increases Signal Density Again with Analog Over Array™
by Mike Gianfagna on 10-04-2023 at 6:00 am

Samtec Increases Signal Density Again with Analog Over Array™

Samtec is well-known for its innovative signal channel solutions. Whether the application requires copper or fiber, Samtec can deliver incredible performance and flexibility. The quality of the company’s models, eval kits and design support are well-known. There is another aspect of Samtec’s innovation. I touched on it in… Read More


Transformers Transforming the Field of Computer Vision

Transformers Transforming the Field of Computer Vision
by Kalar Rajendiran on 10-03-2023 at 10:00 am

The Structure of a Transformer: Attention

Over the last few years, transformers have been fundamentally changing the nature of deep learning models, revolutionizing the field of artificial intelligence. Transformers introduce an attention mechanism that allows models to weigh the importance of different elements in an input sequence. Unlike traditional deep learning… Read More


Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology

Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology
by Daniel Nenni on 10-03-2023 at 6:00 am

blog sept pic1

With the increasing on-chip integration capabilities, large scale electronic systems can be integrated into a single System-on-Chip or SoC. New manufacturing test challenges are raised for more advanced technology nodes where both quality and cost during testing are affected. A typical parameter is test coverage which impacts… Read More


Cyber-Physical Security from Chip to Cloud with Post-Quantum Cryptography

Cyber-Physical Security from Chip to Cloud with Post-Quantum Cryptography
by Kalar Rajendiran on 10-02-2023 at 10:00 am

Secure IC Product Tree

In our interconnected world, systems ranging from smart cities and autonomous vehicles to industrial control systems and healthcare devices have become everyday components of our lives. This fusion of physical and digital systems has led to a term called cyber-physical system (CPS). Ubiquitous connectivity is exposing the… Read More


Extension of DUV Multipatterning Toward 3nm

Extension of DUV Multipatterning Toward 3nm
by Fred Chen on 10-02-2023 at 8:00 am

Extension of DUV Multipatterning Toward 3nm

China’s recent achievement of a 7nm-class foundry node using only DUV lithography [1] raises the question of how far DUV lithography can be extended by multipatterning. A recent publication at CSTIC 2023 indicates that Chinese groups are currently looking at extension of DUV-based multipatterning to 5nm, going so far… Read More


The True Power of the TSMC Ecosystem!

The True Power of the TSMC Ecosystem!
by Daniel Nenni on 10-02-2023 at 6:00 am

logo chart 092623

The 15th TSMC Open Innovation Platform® (OIP) was held last week. In preparation we did a podcast with one of the original members of the TSMC OIP team Dan Kochpatcharin. Dan and I talked about the early days before OIP when we did reference flows together. Around 20 years ago I did a career pivot and focused on Strategic Foundry Relationships.… Read More


Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper

Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper
by Robert Maire on 10-01-2023 at 6:00 pm

china 800 pound gorilla
  • The memory down cycle is longer/deeper than many thought
  • The recovery will be slower than past cycles- a “U” rather than “V”
  • AI & new apps don’t make up for macro weakness
  •  Negative for overall semis & equip- Could China extend downcycle?
Micron report suggests a longer deeper down cycle
Read More

Podcast EP185: DRAM Scaling, From Atoms to Circuits with Synopsys’ Dr. Victor Moroz

Podcast EP185: DRAM Scaling, From Atoms to Circuits with Synopsys’ Dr. Victor Moroz
by Daniel Nenni on 09-29-2023 at 10:00 am

Dan is joined by Dr. Victor Moroz, a Synopsys Fellow engaged in a variety of projects on leading edge modeling Design-Technology Co-Optimization. He has published more than 100 technical papers and over 300 US and international patents. Victor has been involved in many technical committees and is currently serving as an Editor… Read More