How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROIAs computing expands from data centers to edge…Read More
Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V CoresAkeana Inc. announced a key milestone in the…Read More
An AI-Native Architecture That Eliminates GPU InefficienciesA recent analysis highlighted by MIT Technology Review…Read More
Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon SecurityIn a significant advancement for the semiconductor industry,…Read More
Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic EngineeringAt the 2026 Chiplet Summit, Synopsys presented a…Read MoreCEO Interview with Jon Kemp of Qnity
Jon Kemp is President of the Electronics division for DuPont and Chief Executive Officer-Elect for Qnity, the planned independent Electronics Company, which will be an independent, publicly traded company spun off from DuPont’s (NYSE: DD) Electronics business upon completion of the intended separation on November 1, 2025.… Read More
Griffin Securities’ Jay Vleeschhouwer on EDA Acquisitions and Startups
Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, is a noted financial analyst who does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). This year was no exception. He and I spent a memorable afternoon discussing the Synopsys-Ansys merger and startups. … Read More
Security Coverage: Assuring Comprehensive Security in Hardware Design
As hardware systems become increasingly complex and security threats grow more sophisticated, ensuring robust hardware security during the pre-silicon phase of development is more critical than ever. Cycuity’s white paper outlines how its Radix platform enables engineers to verify, visualize, and measure the effectiveness… Read More
Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC
3D IC was a very popular topic at DAC. The era of heterogeneous, multi-chip design is here. There were a lot of research results and practical examples presented. What stood out for me was a panel at the end of day two of DAC that was hosted by Siemens. This panel brought together an impressive group of experts to weigh in on what was really… Read More
Analysis and Exploration of Parasitic Effects
With advanced semiconductor processes continuing to shrink, the number and complexity of parasitic elements in designs grows exponentially contributing to one of the most significant bottlenecks in the design flow. Undetected parasitic-induced issues can be extremely costly, often resulting in tape-out delays.
Silvaco… Read More
Siemens Proposes Unified Static and Formal Verification with AI
Given my SpyGlass background I always keep an eye out for new ideas that might be emerging in static and formal verification. Whatever can be covered through stimulus-free analysis reduces time that needn’t be wasted in dynamic analysis, also adding certainty to coverage across that range. Still, advances don’t come easily. … Read More
Edge Roughness Differences Among EUV Resists
EUV resists are a key component in the implementation and optimization of EUV lithography. By converting a limited number of absorbed EUV photons into a variable number of released migrating electrons, the resist becomes the final determinant of resolution. There are two kinds of resist which are seriously considered: chemically… Read More
Memory Innovation at the Edge: Power Efficiency Meets Green Manufacturing
By Tetsu Ho
With the ever-increasing global demand for smarter, faster electronic systems, the semiconductor industry faces a dual challenge: delivering high-performance memory while reducing environmental impact. Winbond is meeting this challenge head-on by embedding sustainability into every layer of its operations—from… Read More
Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap
Alchip Technologies, a global leader in high-performance computing (HPC) and AI infrastructure ASICs, has officially launched its 2nm Design Platform, marking a major advancement in custom silicon design. The company has already received its first 2nm wafers and is collaborating with customers on the development of high-performance… Read More


Memory Matters: Signals from the 2025 NVM Survey