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SoC Design Verification Engineer

SoC Design Verification Engineer
by Admin on 08-21-2023 at 1:46 pm

  • Full Time
  • Chengdu, China
  • Applications have closed

Descriptions

  • Independently work on the verification of ASIC functional blocks in terms of verification plan, test bench building up, test case development, simulation, and debugging.
  • Setup environment for IP and chip level verification, including behavior modeling.
  • Responsible for RTL/gate level simulation, code coverage and functional coverage analysis.

Requirements

  • Master’s or above degree in EE/CS related majors, working experience is unlimited.
  • Familiar with UVM Verification.
  • Adept at EDA tools (VCS/NC).
  • Familiar with C/C++, Perl, Python, or other programming language.
  • Knowledge of processor design (ARM or RISC-V) and SOC on-chip bus protocols(AMBA/NOC) is a plus.
  • Knowledge of audio and video interfaces such as MIPI/HDMI/DP/SPDIF/I2S is a plus.
  • Knowledge of interfaces such as USB/PCIe/Ethernet/DDR/SD/eMMC/SPI/CAN is a plus.
  • Knowledge of processor (GPU/CPU) or computer architecture, AI, ISP, or video processing is a plus.
  • Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.
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