This is an opportunity to contribute and innovate in the design of next-generation Memory subsystem Design IPs at Cadence. These advanced technology node IPs will enable the futuristic SoCs for Datacenter, Edge computing, Automotive and AI applications.As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow and primarily, IP and block level synthesis and timing closure ownership throughout the entire project cycle. You would be responsible for generation of block and full chip timing constraints, development and maintaining sign-off methodology and flows related to timing verification and closure across advanced technology nodes.You would also be contributing to futuristic clocking architecture, design micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis. You will be closely interfacing with the internal Physical Design team on STA, timing closure and P&R, and also provide guidance on SoC level timing closure to customers using Cadence IP. This is an opportunity to work and interact with accomplished digital and analog circuit designers and timing experts who has built industry leading multi protocol memory PHYs for over a decade. You will work in a dynamic, team environment and must be an effective team player on projects. You will have ample opportunities to expand your knowledge, expertise and skillset. You may interact with marketing, support, verification, sales, and customers.
- BSEE and at least 10 years of prior experience required. MSEE and at lest 5 years of prior experience strongly preferred.
- Prior experience in timing or RTL design of high-speed interfaces.
- Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
- Thorough knowledge of the IP/SoC level timing closure flow and methodology.
- At least 3+ years’ experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow
- Knowledge of timing corners/modes, process variations and signal integrity related issues, SOCV/AOCV.
- Hands on experience in timing constraints generation and management
- Proficiency in scripting languages (TCL and Perl)
- Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools
- Capability to understand and implement improvements to existing methodologies and flows.
- Strong background in Constraint analysis and debug, using industry standard tools.
- Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.
- Team player with a passion to innovate and can-do attitude.
- Self-starter and highly motivated.
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To view the job application please visit cadence.wd1.myworkdayjobs.com.