Job ID #: 18465
Job Category: Hardware Engineering
Employment Type: Experienced Professionals
Division: Central Engineering – CPU
Department: Central Engineering – CPU Engineering
Primary Country: France
Primary Location: Sophia Antipolis
Do you want to help Arm and its partners to build outstanding products?
Arm’s Sophia Antipolis design centre is located in one of the most appealing parts of France, at the heart of Europe’s largest and most dynamic technology park. Surrounded by mountains and the Mediterranean Sea, this exceptional design center has delivered leading products from Arm’s Cortex (TM) processor family. These CPUs power some of the world’s best-selling smartphones, tablets and gaming systems, using technology that has taken user experience and performance to another level.
Now, you have an opportunity to work on the next generation of processors that will appear in the most desirable products over the next 3 years. The Local design team is a good combination of very expert engineers and some of the most enthusiastic and hardworking graduates, coming from the best engineering schools. Collectively, the team is highly creative, collaborative, delivery orientated and committed.
Meeting Area, Frequency and Power requirements is one of the most meaningful activities in microelectronics development. We work in a close loop with micro-architecture designers and standards cells/Macro designers to build and improve metrics as well as the overall quality of designs targeting 7nm and below technology nodes. Using a broad array of skills, we are also taking ownership of a complete implementation flow development from synthesis to GDSII, including static timing analysis, IR drop analysis and equivalence checking.
As a member of our implementation team, you will:
- Work together with IP design team to identify critical paths and timing bottlenecks across IP development, enabling accurate trade-off between the various performance metrics of the designs (frequency, IPC, power, area)
- You will have to produce Power/Performance/area figures and help to improve CPU and machine learning accelerators microarchitecture
- You will participate in existing products benchmarking to get the best possible Quality of Results
Education & Qualifications
- Graduate from a University or Engineering School, in Electronic Engineering or Computer Science with first experience/exposure on ASIC design flow would be beneficial.
- Experienced professional with previous work in power/area/timing improvement of CPU, GPU, SOC or related IP
Essential Skills & Experience
- knowledge on synthesis/floor-planning/power planning, clock tree, place and route tools and techniques
- Understanding of Power versus Performance versus Area tradeoff in typical CMOS design
- Verilog or VHDL or System Verilog knowledge
- Ability to schedule own workload and plan tasks
- Good interpersonal skills
Desirable Skills & Experience
- Knowledge of CPU, GPU, Machine learning accelerator micro-architecture concepts
- Able to work in French and in English
- Knowledge of power domain management through UPF
- First exposure to advanced process nodes (16nm and below) and advanced timing analysis concept (OCV, AOCV, noise propagation)
- Understanding of DFT techniques and goals
- Experience of developing scripts (Python, Perl, tcl …) for automation purpose
- Prior internship in SOC implementation, Sign-off or test can be an advantage
- Working in UNIX/Linux environment, with bug tracking and source code control systems, especially GIT
- Salary – depending on experience
- Discretionary Cash Awards
- Private Medical Insurance
- Permanent Health Insurance
- Life Assurance
- Contributory Pension
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