Job Description: Work with expert team to design and deliver interconnect and memory hierarchy solutions for sophisticated telecommunications, automotive, and consumer System-on-Chip (SoC) products; Model complex configurable designs and conduct performance analyses to drive architectural decisions; Conduct client performance analyses for NCore products; Develop and maintain C++ and SystemC models for Network-on-chip (NoC) products; Implement functional blocks, add new product features, construct benchmarks, and test and debug to ensure functional and timing correctness of NCore system performance models; Collaborate with cross-functional teams, including Architecture, RTL Design, and Software to profile use cases and highlight in C++ models; Perform performance simulations and measure for alternative designs; Analyze workloads to identify performance bottlenecks and opportunities; Correlate performance of RTL with C++ models and document architectural performance models; Identify innovative ways to improve product bandwidth, latency, area, and power.
Requirements: Position requires a Bachelor’s degree in Computer Engineering, Electrical Engineering, or closely related technical discipline and 2 years of industry experience, specifically with semiconductor product design. Alternatively, will accept a Master’s degree in Computer Engineering, Electrical Engineering, or a closely related technical discipline and no experience.
Requires education or experience in each of the following: Network-on-Chip (NoC) cache coherence protocols, including MOESI and computer architecture; Chip design through architecture, logic design, verification, synthesis, place and route, timing analysis; System-on-Chip (SoC) performance metrics, like bandwidth, latency, power, area; System-on-Chip (SoC) performance measurement and analysis; Software engineering, programming, and debugging through C/C++, SystemC/TLM; Scripting languages, including Python and Perl; Performance modeling protocols including Loosely Timed (LT) modeling and Approximately Times (AT) modeling; RTL and TLM correlation; Hardware design verification and logic design flow; Document technical specification.
To Apply Send Resume to: HR Recruiting, Arteris, 595 Millich Dr., Ste 200, Campbell, CA 95008.
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To view the job application please visit www.arteris.com.