Responsible for leading the design of key functional blocks (read/write circuits in the memory array, data path and buffer circuits, on-chip supply voltage system, analog circuits, fault tolerant circuits) in memory testchip and memory IP.
The candidate will also lead the definitions of memory architecture, application spec and testing requirements.
– Lead the design of custom read and write circuits in memory macro
– Lead the design of low-power sense amplifier, write circuitry, on-die LDO circuit and supply voltage system.
– Lead the design of fault-tolerant circuits, including repair and error correction circuit, and built-in-self-test (BIST) circuit.
– Evaluate and optimize memory architecture
– Drive testing methodology, silicon testing and debug.
– MST or PhD degree in Electrical Engineering
– 5+ years’ experiences on memory circuit design or memory technology development.
– Expertise in development of emerging memory as well as the custom macros of all types: SRAM, MRAM, RRAM, DRAM, NAND
– Knowledge of industry standard circuit, design and integration tools.
– Experience with variation-aware design in nano-meter technology nodes.
– Experience with tight pitch-matched memory circuit and layout designs.
– Technical expertise on CMOS digital, analog, and memory circuit design using commercial TCAD tools.
– Familiar with testing setup, silicon testing and debug.
– Having a good track record on delivering memory testchips, products or memory technology development is a plus.
– Good knowledge on memory product design and physical design methodologies. Experience on memory product development is a plus.
– Fluent in either Chinese and English.
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To view the job application please visit tsmc.taleo.net.