– Design full custom read and write circuits at transistors level
– Simulate and analyze the circuit design using transistor level simulators.
– Extract the layout and perform post-layout simulations and verification
– Floorplan physical implementation and leafcell layout integration to build the physical macro
– Integrate characterization flow to extract timing and power information
– Develop scripts to automate characterization flow, simulations, and verification
– Document the design specifications, behavioural description, and timing diagrams
– Help specify silicon test plan and correlate silicon to simulation data
– Design sense amplifier, on-die LDO circuit and power supply system.
– Expertise in development of emerging memory or custom macros of all types: SRAM, MRAM, RRAM, DRAM and NAND
– Good understanding of transistor-level circuit behavior and device physics
– Experience with tight pitch-matched memory layout designs
– Technical expertise on CMOS digital, analog, and memory circuit design using commercial simulators and verification tools.
– Good understanding of memory behavioral and physical models
– Good understanding of DFT schemes and chip level integration
– Familiar with test setups, silicon testing and debug
– Proficient in running simulators, writing automation scripts
– Logical thinking.
– Good analytical and problem solving skills.
– Strong execution mind-set
– Good communication, interpersonal, and leadership skills
– Motivated, self-driven and good at multi-tasking.
– Fluent in either Chinese and English
Apply for job
To view the job application please visit tsmc.taleo.net.