The candidate is expected to have knowledge of C modeling and expertise in SV based verification environment. He/she must possess good analytical and communication skills.
- BE (Electronics / Computer Science) from a reputed institute with 4-7 years of experience
- Experience in Verilog/System Verilog/UVM/C
- Experience with development and verification using SV, UVM and C will be a plus.
This position requires leading VIP product development and becoming technical expert in protocol and standard methodologies such as UVM. The position requires excellent communication skills to interact with multiple product groups within Cadence and the ability to ramp up on new technologies quickly and independently.
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