The job involves development of the Assertion Based Verification IPs for Cadence’s JasperGold Formal Verification tool. This person will work as an individual contributor responsible for design & implementation of the ABVIPs.
Bachelor’s Degree + 5 or more years industry experience or Masters with 3 or more years of experience as a Design Verification engineer.
– Very good understanding of HDLs (Verilog, System Verilog) is MUST
– Protocol knowledge like (AHB,AXI,APB,CHI,I2C) is MUST
– Very strong RTL design and synthesis concepts is required
– Very good understanding of System Verilog Assertion is required
– Strong analytical and problem solving skills required
– Hands on experience with HVL and VIP required
– Formal verification knowledge will be plus
– Experience in process automation with PERL/Tcl/Python scripting will be plus
– He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
– He/ she should have good communication skills.
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To view the job application please visit cadence.wd1.myworkdayjobs.com.