ASIC Digital Design Engr, II

Job Description and Requirements

Seeking a digital verification engineer with exceptional theoretical and practical background in high-speed data recovery circuits. Working as part of a experienced mixed-signal design team, the candidate will be involved in verifying next generation PAM and NRZ SERDES products spanning multiple protocols like Ethernet and PCIe. The position offers an excellent opportunity to work with experienced team of digital and mixed signal engineers accountable for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips.

Responsibilities of this job include:

• Writing modular constrained-random verilog and system-verilog testbenches.
• performing functional coverage,
• assertion coverage, and code coverage;
• creating and tracking testplans;
• evaluating failure cases and running gate-level simulations.

Key Qualifications:

• MSEE with some digital verification industry experience
• Hands-on experience in writing complex testcases in Verilog and System Verilog,
• Must have familiarity with code quality metrics.

Preferred Experience:

• Knowledge of the following:
• high-speed digital & mixed-signal design
• asynchronous clock crossings
• DFT design methodologies