Xilinx the EDA Company

Like you I cannot believe 2015 is upon us. 15 years ago I remember the Y2K panic. I remember watching the news and noticed the liberal media (they were liberal back then too) just waiting for the first fail somewhere. Ended up like Geraldo at the opening of Al Capone’s Vault. Remember that one? As I persist on with this word salad may I be the first to wish you a Merry Christmas?

I just witnessed again, Uncle Billy giving the 8 grand to Mr. Potter (It’s a Wonderful Life), drives me nuts every time. I better write something techy here, I’m losing you. Happy New Year as well!

In 2014, Xilinx quietly solidified its global lead for the next decade by finalizing what I would call a morph from a fabless FPGA company, to a fabless SoC + EDA company. Did you catch that morph? It has been an ongoing execution since Moshe became CEO of Xilinx in 2008. Moshe took the helm of a great company with the challenge of making Xilinx even greater. Having an EDA background (which Moshe had coming from Cadence) did not hurt.

Not by chance but by Xilinx strategy they acquired AutoESL (which developed a tool called Autopilot; the 1[SUP]st[/SUP] ‘C to gates’ tool that worked great in my opinion). Xilinx rolled AutoPilot into Vivado calling it Vivado HLS. I keep banging this drum but here is where an FPGA could ‘really’ be programmed using C/C++. The figure below is not marketing propaganda but reality. Xilinx had the foresight that a programming model beyond RTL would be needed.

While all this is going on Xilinx ISE circa 1995 (plus many updates along the years) was not going to get a face lift but a morph as well (or burial of sorts). It started by throwing the ISE Place and Router (P&R) away and designing a new one from scratch just like grandma did. There was just no way simulated annealing was going to yield reliable P&R times nor efficient FPGA usage with 4M+ Logic Cells in view. Vivado was born using analytic place and route which yields this fantastic before and after as shown below.

Speaking of another birth, the Millers are expecting another in March 2015, of the male kind. For earned value I have already taken credit for the birth in the FYI 2014. For those of you counting this will be Child number 8, Lord willing.

2015 will be the year of ‘16’, nanometer that is. But more than that, Xilinx recently announced ‘SDAccel’:

· First Architecturally Optimizing Compiler for OpenCL, C, and C++
· First Complete CPU/GPU Like Development Experience on FPGAs
· First Complete CPU/GPU Like Run-time Experience on FPGAs

This video does a great job on explaining what SDAccel is all about.

Xilinx brought to the world the first ARM SoC FPGA named Zynq. Software engineers once alienated from FPGAs found themselves where hardware engineers lived, except from a different view. This is the grand unification of Xilinx FPGAs into all systems, and I mean all. SDAccel is not just another ‘tool’ in the ‘tool box’ but the very fabric that will allow Xilinx FPGAs to live in data centers, IoT, Military Systems and where CPUs/GPUs are embedded but no longer are affordable options. The table below from theLinley Group does a great job highlighting the Xilinx SDAccel significant advantages. Like I said in July, RIP CPU.

The C/C++, OpenCL programming model for FPGAs is here to stay and Xilinx has the edge not only in silicon but with tools as well. Wait ’til you see 2015 from Xilinx…. I cannot wait!