TSMC's Risky Bet Could Be Great News for Intel Investors

[Daniel Nenni]

Taiwan Semiconductor Manufacturing (NYSE: TSM), the world's largest contract chipmaker, produces the world's smallest, densest, and most power-efficient chips. That makes it a bellwether of the semiconductor industry and a crucial partner for fabless chipmakers like Apple, Advanced Micro Devices, and Nvidia.

However, TSMC wouldn't have sprinted ahead of Intel (NASDAQ: INTC) and Samsung in the "process race" to manufacture more advanced chips without the Dutch semiconductor equipment maker ASML (NASDAQ: ASML), the world's leading producer of lithography systems for etching circuit patterns onto silicon wafers. TSMC's earlier adoption of ASML's extreme ultraviolet (EUV) lithography systems enabled it to produce the world's tiniest chips.

Image source: Getty Images.

TSMC started to mass produce its smallest 3 nanometer chips in late 2022, and it plans to start mass producing its 2nm chips in 2025. But to manufacture chips with processors smaller than 2nm, TSMC will likely need to use ASML's new high-NA (numerical aperture) EUV systems. That's why it was surprising when analysts at China Renaissance and SemiAnalysis recently claimed TSMC wouldn't actually start adopting those high-NA EUV systems until after 2030.

Meanwhile, Intel -- which aims to catch up to TSMC and Samsung in the process race by 2025 -- has already been installing its first high-NA systems at its foundries. Therefore, TSMC's decision seems like a risky move that could narrow its competitive moat. But for Intel, this could represent a golden opportunity to gain some ground against TSMC.

Why isn't TSMC upgrading its EUV systems?​

TSMC isn't rushing to upgrade its systems for three reasons. First, it already spent billions of dollars on its existing EUV systems, which were first used to mass produce its chips back in 2019. A single EUV system costs about $200 million, is shipped in pieces via multiple planes, and requires additional training to use.

TSMC likely believes there's still a lot of mileage left in these systems, and it could push the technology to the limit to manufacture high-end chips for a lower cost than high-NA systems through the end of the decade. That's what it previously did with ASML's older deep ultraviolet (DUV) systems (up to the 7nm node) before switching over to EUV systems.

Second, TSMC's earlier adoption of ASML's EUV systems was partially subsidized by Apple, which was shifting its production away from Samsung at the time and needed the Taiwanese chipmaker to mass produce its top-tier chips. TSMC had actually been reluctant to adopt the expensive technology before Apple stepped in.

Once again, TSMC seems reluctant to adopt ASML's latest systems. But this time, there's no guarantee Apple will subsidize those purchases -- and the recent rumors suggest the tech giant won't foot the bill for the chipmaker's high-NA upgrades.

Lastly, TSMC might be trying to avoid a bidding war that might erupt between Intel and Samsung for ASML's first batch of high-NA systems, which each cost over $300 million. Spending too much money on installing new high-NA systems over the next few years could disrupt its current development roadmap for its 3nm and 2nm chips.

Why does this represent an opportunity for Intel?​

Intel is already installing ASML's high-NA systems, but it won't actually deploy the machines to mass produce its chips until a few years down the road. Intel expects to continue using ASML's EUV systems up until its 18A (1.8nm) node, which should be comparable to the density of TSMC's 3nm node when it arrives in the second half of 2024.

But beyond the 18A node, Intel plans to start using its high-NA systems to produce smaller chips. That means it will start producing its equivalent of TSMC's 2nm chips with high-NA EUV systems while TSMC continues using its low-NA systems.

In February, Intel will reveal its full post-18A roadmap. I believe it will reiterate its commitment to ramping up its near-term spending to pull ahead of TSMC and Samsung with denser and more power-efficient chips -- and its earlier investments in high-NA systems could give it an edge against its two Asian rivals over the long term.

For now, Intel's investors are likely focused on the cyclical recovery of the PC market, which should finally stabilize its sales of desktop and laptop CPUs this year. But looking further ahead, Intel's investors should focus on the company's decision to adopt high-NA EUV systems years before TSMC -- and how that move might help it regain the process lead, win over more fabless chipmakers, and make it a compelling long-term investment once again.

TSMC's Risky Bet Could Be Great News for Intel Investors

The Taiwanese chipmaking giant could be making a generational mistake.

www.yahoo.com

 

[Daniel Nenni]

Complete nonsense. TSMC is ASML's largest and closest collaborating customer. I can assure you there is a strategy behind this High NA decision. Expect nothing less from C.C.Wei. Hopefully there will be a question about this on the next investor call that will clear things up and prove these questionable sources wrong.

This guy is completely off base here:

Why isn't TSMC upgrading its EUV systems?
TSMC isn't rushing to upgrade its systems for three reasons. First, it already spent billions of dollars on its existing EUV systems, which were first used to mass produce its chips back in 2019. A single EUV system costs about $200 million, is shipped in pieces via multiple planes, and requires additional training to use.

TSMC likely believes there's still a lot of mileage left in these systems, and it could push the technology to the limit to manufacture high-end chips for a lower cost than high-NA systems through the end of the decade. That's what it previously did with ASML's older deep ultraviolet (DUV) systems (up to the 7nm node) before switching over to EUV systems.

Second, TSMC's earlier adoption of ASML's EUV systems was partially subsidized by Apple, which was shifting its production away from Samsung at the time and needed the Taiwanese chipmaker to mass produce its top-tier chips. TSMC had actually been reluctant to adopt the expensive technology before Apple stepped in.

Once again, TSMC seems reluctant to adopt ASML's latest systems. But this time, there's no guarantee Apple will subsidize those purchases -- and the recent rumors suggest the tech giant won't foot the bill for the chipmaker's high-NA upgrades.

Lastly, TSMC might be trying to avoid a bidding war that might erupt between Intel and Samsung for ASML's first batch of high-NA systems, which each cost over $300 million. Spending too much money on installing new high-NA systems over the next few years could disrupt its current development roadmap for its 3nm and 2nm chips.

 

[blueone]

It is unfortunate that Yahoo Finance has become almost as much of a junk news site as CNBC. Yahoo used to be better. In fact, they would have surpassed CNBC's clickbait factor if not for the fact that CNBC has been on an accelerated path to being almost completely clickbait. Bloomberg has declined in article quality too, where you can't tell the difference between their editorials and their "news" articles. The Wall Street Journal is not far behind Bloomberg, but is more conservative-leaning and at least the news reporting is less editorialized, but the WSJ expanded their lifestyle, real estate, and fashion articles to the point where they're becoming obnoxious.

If a person is looking for financial analysis for high-tech, and especially semiconductors, there aren't many sources of objective expert analysis. Some of my non-technical friends occasionally forward me articles from Zacks and The Motley Fool, and they're useless too, if anything misleading. My brokerage firm's rating system for technical companies is laughable. Very disappointing.

 

[nghanayem]

Complete nonsense.

Thanks for the Monday funny paper Dan .

TSMC is ASML's largest and closest collaborating customer.

Largest definitely especially with how little litho NAND uses and the fewer mask layers in a full DRAM chip. Closest collaborating seems like they are at best tied with the new intel. But with high-NA it seems like intel has taken the leadership position on collaborating with ASML on development. Of course I am not privy to what happens at IMEC behind closed doors nor the goings on at Fab12, and I would not be shocked if TSMC is engaging in comparable levels of research activity with ASML/ROW.

I can assure you there is a strategy behind this High NA decision. Expect nothing less from C.C.Wei. Hopefully there will be a question about this on the next investor call that will clear things up and prove these questionable sources wrong.

Everyone does. Albeit Samsung seems the least clear to me in their intentions. But that might be just due to how uncertain things seem at Samsung logic. Assuming TSMC is buying at least one or more likely two tools that seems inline with my expectations. Intel buying 6 tools is kind of whatever. It's not like Oregon, Ohio, and Germany are going to get filled off of six tools (this number which is in of itself a rumor) unless they plan to only use one scanner for each of those new fabs and two for the whole of D1. IF the number is right that just lets intel make one mean pilot line at D1. As long as TSMC has enough for their development and pilot line that is good enough. TSMC doesn't upgrade old fabs to new process technologies so it's always weird to me when folks talk about the existing TSMC EUV fleet. When those A14 and A10 fabs get built out you can bet your biscuits that this is when TSMC will buy a ton of high-NA steppers (assuming they see benefit in doing so vs more advanced low NA MP schemes). Until then why bother buying anything more than the small number that Fab12 needs?

 

[hist78]

Does anyone know when the High NA Systems from ASML will be ready for real world fab production?

Or, when will Intel start using high NA for high volume production?

TSMC had some ASML EUV machines several years before it finally applied it to N7+ production in 2019.

 

[hist78]

Thanks for the Monday funny paper Dan .

Largest definitely especially with how little litho NAND uses and the fewer mask layers in a full DRAM chip. Closest collaborating seems like they are at best tied with the new intel. But with high-NA it seems like intel has taken the leadership position on collaborating with ASML on development. Of course I am not privy to what happens at IMEC behind closed doors nor the goings on at Fab12, and I would not be shocked if TSMC is engaging in comparable levels of research activity with ASML/ROW.

Everyone does. Albeit Samsung seems the least clear to me in their intentions. But that might be just due to how uncertain things seem at Samsung logic. Assuming TSMC is buying at least one or more likely two tools that seems inline with my expectations. Intel buying 6 tools is kind of whatever. It's not like Oregon, Ohio, and Germany are going to get filled off of six tools (this number which is in of itself a rumor) unless they plan to only use one scanner for each of those new fabs and two for the whole of D1. IF the number is right that just lets intel make one mean pilot line at D1. As long as TSMC has enough for their development and pilot line that is good enough. TSMC doesn't upgrade old fabs to new process technologies so it's always weird to me when folks talk about the existing TSMC EUV fleet. When those A14 and A10 fabs get built out you can bet your biscuits that this is when TSMC will buy a ton of high-NA steppers (assuming they see benefit in doing so vs more advanced low NA MP schemes). Until then why bother buying anything more than the small number that Fab12 needs?

I remembered Pat Gelsinger said that each new Intel fab needs at least 12 EUV machines.

 

[hskuo]

Does anyone know when the High NA Systems from ASML will be ready for real world fab production?

Or, when will Intel start using high NA for high volume production?

TSMC had some ASML EUV machines several years before it finally applied it to N7+ production in 2019.

From ASML's plan: To support HVM in 2025-2026, but it is doubtable.

2. Look at EUV's history, it takes more than 10 years to develop EUV technology to HVM. There are several technology evolutions in Hi NA EUV tool. Will the Hi NA HVM tool be ready in 5 years? It could be doubtable also.

 

[hskuo]

I remembered Pat Gelsinger said that each new Intel fab needs at least 12 EUV machines.

This will depend on Hi NA EUV daily output, capacity plan and EUV layers in intel fab process. Ballpark estimation, 12 EUV tools might support ~20/25kwpm capacity for logic technology.

 

[Fred Chen]

High-NA EUV requires multiple (at least two, often 3) reticle passes to pattern the same wafer field as other lithographic systems. This is already true for Meteor Lake (compute tile). A faster pass to keep throughput requires higher power to keep the same dose. They will need >800W, and that's tough for pellicles.

 

[hskuo]

High-NA EUV requires multiple (at least two, often 3) reticle passes to pattern the same wafer field as other lithographic systems. This is already true for Meteor Lake (compute tile). A faster pass to keep throughput requires higher power to keep the same dose. They will need >800W, and that's tough for pellicles.

Fred: Chip needs stitch of Hi NA EUV reticles is only when the die size is larger than half of reticle size (26x33mm2). It seems compute tiles of Meteor Lake do not have the size larger than that. Besides, Meteor Lake is manufactured by intel 4 technology which might not need Hi NA EUV patterning. FYI.

 

[Fred Chen]

Fred: Chip needs stitch of Hi NA EUV reticles is only when the die size is larger than half of reticle size (26x33mm2). It seems compute tiles of Meteor Lake do not have the size larger than that. Besides, Meteor Lake is manufactured by intel 4 technology which might not need Hi NA EUV patterning. FYI.
View attachment 1607

The 26mm x 33 mm field would be filled out with 3 x 3 Meteor Lake dies to maximize productivity, but the High-NA would only be able to scan a single row 1 x 3; it would need three of these to give 3 x 3. I only use Meteor Lake as a representative die size example.

 

[nghanayem]

High-NA EUV requires multiple (at least two, often 3) reticle passes to pattern the same wafer field as other lithographic systems. This is already true for Meteor Lake (compute tile). A faster pass to keep throughput requires higher power to keep the same dose. They will need >800W, and that's tough for pellicles.

Question for your Fred. The field issue is pretty well reported, but I remember ASML marketing high-NA as faster than low-NA for a given feature. I thought that the higher NA increased the rate of dose being delivered at same power. Is this understanding flawed? Based on what is floating around the web, I was under the impression that the main application of high-NA would be doing things like 30-28nm direct print with a high enough throughput to be more cost effective than SALELE (once the ecosystem is able to improve blur, resists, and the like to a mature level ofc).

 

[Fred Chen]

Question for your Fred. The field issue is pretty well reported, but I remember ASML marketing high-NA as faster than low-NA for a given feature. I thought that the higher NA increased the rate of dose being delivered at same power. Is this understanding flawed? Based on what is floating around the web, I was under the impression that the main application of high-NA would be doing things like 30-28nm direct print with a high enough throughput to be more cost effective than SALELE (once the ecosystem is able to improve blur, resists, and the like to a mature level ofc).

They have some system changes to improve throughput, but nothing inherent about higher NA.

In fact, throughput will go down at same power, for the following two reasons:

1. More reticle scans needed to fill the 26 mm x 33 mm field. It's not the single die size, but the multi-die that matters.
2. Higher doses due to thinner resist absorbing less. This is from resist pattern collapse as well as depth of focus.

 

[nghanayem]

They have some system changes to improve throughput, but nothing inherent about higher NA.

That I was aware of, but I had always thought throughput was exposure limited. Guess you can still get big improvements from the stepper.

In fact, throughput will go down at same power, for the following two reasons:

1. More reticle scans needed to fill the 26 mm x 33 mm field. It's not the single die size, but the multi-die that matters.
2. Higher doses due to thinner resist absorbing less. This is from resist pattern collapse as well as depth of focus.

Metal oxide resits seem to be a key enabler for both better low and especially high-NA EUV. From your ear to the ground does it sound like widespread adoption may be imminent or is it still a long ways off? Either way it sounds like high-NA's only real path to economic viability is improving effective resolution at iso DD to the point that it can at least compete with (x+1) low-NA multi patterning (with x being the number of high-NA passes) on cost.

 

[Fred Chen]

That I was aware of, but I had always thought throughput was exposure limited. Guess you can still get big improvements from the stepper.

Metal oxide resits seem to be a key enabler for both better low and especially high-NA EUV. From your ear to the ground does it sound like widespread adoption may be imminent or is it still a long ways off? Either way it sounds like high-NA's only real path to economic viability is improving effective resolution at iso DD to the point that it can at least compete with (x+1) low-NA multi patterning (with x being the number of high-NA passes) on cost.

High-NA productivity needs the kW-level power, but the pellicles can't take it. 20 nm thick MOR is only absorbing 33%, so we're pushing 100 mJ/cm2.

 

[nghanayem]

High-NA productivity needs the kW-level power, but the pellicles can't take it. 20 nm thick MOR is only absorbing 33%, so we're pushing 100 mJ/cm2.

I might be misunderstanding how this works Fred so please correct me if I am wrong. So you have your power, your dose (which is determined by power*exposure time), and the speed of the stepper impacting throughput. Stepper speed is partially offset by platform improvements which will probably eventually go to the low-NA steppers anyways and doesn't completely offset the extra exposures and associated movement with the smaller field size hurting throughput. To get those higher effective resolutions you'd need to make a strong business case, you need more dose to deal with the stochastics. If you wanted to do this without further gimping speed you would need to boost power. This is something which the pelicales and CAR resists can't currently handle and MOR resists absorb too little. If you just accept that effective throughput of the system will be like 1/3 or 1/4 of low-NA tool can you just get that effective resolution with longer exposures? Because if that is the case I think it might be possible to get a good ROI if you look beyond individual scanners to a fab wide cost perspective. If that resolution can't be achieved by sacrificing throughput then I suppose high-NA commercialization is not happening anytime "soon". If that is the case though it seems contrary to the actions of other the ecosystem.

 

[Fred Chen]

I might be misunderstanding how this works Fred so please correct me if I am wrong. So you have your power, your dose (which is determined by power*exposure time), and the speed of the stepper impacting throughput. Stepper speed is partially offset by platform improvements which will probably eventually go to the low-NA steppers anyways and doesn't completely offset the extra exposures and associated movement with the smaller field size hurting throughput. To get those higher effective resolutions you'd need to make a strong business case, you need more dose to deal with the stochastics. If you wanted to do this without further gimping speed you would need to boost power. This is something which the pelicales and CAR resists can't currently handle and MOR resists absorb too little. If you just accept that effective throughput of the system will be like 1/3 or 1/4 of low-NA tool can you just get that effective resolution with longer exposures? Because if that is the case I think it might be possible to get a good ROI if you look beyond individual scanners to a fab wide cost perspective. If that resolution can't be achieved by sacrificing throughput then I suppose high-NA commercialization is not happening anytime "soon". If that is the case though it seems contrary to the actions of other the ecosystem.

Yes, it is a little analogous to Tennant's Law: https://lithoguru.com/life/?p=234

Hard to really say. If resolution could override throughput as priority, then e-beam direct write should conceivably have won, especially with its much lower cost of ownership.

 

[nghanayem]

Yes, it is a little analogous to Tennant's Law: https://lithoguru.com/life/?p=234

Hard to really say. If resolution could override throughput as priority, then e-beam direct write should conceivably have won, especially with its much lower cost of ownership.

I had kind of always assumed that high-NA to low would have similar economics to low-NA EUV vs DUV rather than wet vs dry DUV. Where yeah throughput per tool is worse and cost is worse, but overall wafer cost is lower when it is judiciously applied to critical layers by not having all of the other tools, litho exposures, and time wasted shuttling around FOUPs or getting wafers inspected. You bring up an interesting point on E-beam. I had never really thought of how the same logic to justify low or high NA could be applied to e-beam. I remember seeing those old papers about a bank of e-beam tools in the same footprint as an EUV stepper, and now I really want to see somebody crunch the math for e-beam vs high-NA for high resolution direct print. I don't really know or think there is a ton of academic or industry interest so maybe the math is still not good enough to consider it as an alternative to high-NA either. I know Tanj is an E-beam connoisseur, so maybe he has a better ear to the ground on if there is any interest in using E-beam instead of high-NA (direct print or SALELE) or more complex low-NA multipatterning schemes.

 

[MKWVentures]

@nghanayem @Daniel Nenni @Fred Chen

Since we all agree that Intel3 is not 3nm and 20A is not 2nm.... and that the same is true for TSMC.

What is the minimum feature / half pitch on Intel 3 and 20A?
What is the minimum feature/ half pitch on TSMC N3 and N2?
What is the smallest feature (half pitch) that .33 EUV can print directly (before pitch doubling/quadrupling)?

is this a @Scotten Jones question?

thanks for the help

 

[nghanayem]

@nghanayem @Daniel Nenni @Fred Chen

Since we all agree that Intel3 is not 3nm and 20A is not 2nm.... and that the same is true for TSMC.

What is the minimum feature / half pitch on Intel 3 and 20A?
What is the minimum feature/ half pitch on TSMC N3 and N2?

Min feature is a bit too generic a question. For example the width of a single fin on N5 is single digit nm and Gox thickness was like 5 atoms thick pre high-K. It wouldn't surprise me if it is back to being sub nanometer for advanced high-K nodes like N3B.

But assuming you mean min metal pitch or fin/min nanosheet pitch: i3, 20A, and N2 are not publicly known. From memory N3B M0 pitch from white papers is 23nm. Can't recall if N3E is either presumed or known to have a 28nm M0 pitch. Given techinsights is a paid for service and I don't know if any of their N3 coverage is out there for free (I think they have some of it out there for folks without a subscription), I don't want to quote their numbers here. Since I can freely speculate on N2. My gut says N2 has the same minimum CDs as N3E with the density shrink coming from libraries being similar in size to a bit shorter than with N3B. This would be due to the higher drive per unit area of GAAFET vs finFET. My bet is that the HP lib is similar in size to a 2 fin and the HD lib is smaller than the 2 fin and similar to the size of the 1 fin lib. I'm guessing they will also use a 48nm pp like N3E.

What is the smallest feature (half pitch) that .33 EUV can print directly (before pitch doubling/quadrupling)?

Fred has said ~36nm for 1.5D directprint, and I think the current min was Samsung doing 30nm unidirectional direct print back in like 2021. As for when double becomes not enough and you have to go to triple and quad depends on the method chosen. If it is LE^n then you have to go to triple and quad pretty fast. If it is pitch multiplication then on paper 15-7.5nm needs SAQP. But if you were doing that you would want to back off on the backbone pitch to reduce LER/stochastics. Also those cuts for a SAQP 7.5nm would be hell. SALE^n I think it is somewhere in the middle.