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ISSCC N2 and 18A has same SRAM Density.

Given that N2 processors will clock higher than this; what kind of SRAM/memory is required for L0/L1 caches on processors to hit 5+ GHz frequencies? (Chart shows 4.2 GHz @ 1.05 volts and 4.5 GHz @ 1.20 volts).

1739983556743.png
 
How do we compare the SRAM speed vs previous nodes. TSMC N5 SRAM was shown as 4.1 GHz @ 0.85V in March 2020: (I can't find any public info for N4 or N3) :

1739996425559.png
 
That's basically like a half-node increase in clock speed for the same voltage! Will be interesting to see how much TSMC's A16 node closes the gap compared to Intel's 18A node.
 
Are those sizes raw memory cell array or overall area including peripheral circuits (decode/sense/drive/muxing)?

I seem to remember seeing elsewhere that these numbers weren't apples-to-apples, TSMC figure was net (including peripheral) and the others were gross (memory cell only), and that in fact TSMC was considerably higher density, but I could be mistaken...
Intel has decoders as well the tweet is a long thread that should provide the details for what you are looking for.
GkKgpYIbUAEmI1M.jpg
 
Intel claiming 18A is ready.
Very nice! What does "being ready" mean exactly?

Intel claims 18A is "The earliest available sub-2nm advanced node manufactured in North America, offering a resilient supply alternative for customers." Reading b/w the lines, this seems to suggest that TSMC N2 is also "ready".
 
Very nice! What does "being ready" mean exactly?

Intel claims 18A is "The earliest available sub-2nm advanced node manufactured in North America, offering a resilient supply alternative for customers." Reading b/w the lines, this seems to suggest that TSMC N2 is also "ready".
I think it means that they are ready for external customer tapeout. They targeted H1 2025. I think they are on schedule till now.
 
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