ISSCC N2 and 18A has same SRAM Density.

[IanCutress]

I think it means that they are ready for external customer tapeout. They targeted H1 2025. I think they are on schedule till now.

First 18A product, internal or external, is Panther Lake, ramping in 2H25. If anything it has been brought in - original projections were late 1H26 back when Pat first started. Then Clearwater Forest ramping in late 2H25 for 1Q26 launch. Turns out if you don't need to chase large dies without defects, stuff can get out the door sooner

 

[siliconbruh999]

@IanD here is the summary for you for Ian's thread

Thread by @IanCutress on Thread Reader App

@IanCutress: Sat in @ieee_isscc session 29: SRAM 1st paper: $TSM 38 Mb/mm2 N2 HD SRAM 2nd paper: $INTC 38 Mb/mm2 18A HD SRAM 3rd paper: @Mediatek 3nm TCAM 4th paper: @Synopsys 38 Mb/mm2 3nm HD SRAM...…

threadreaderapp.com

 

[IanD]

@IanD here is the summary for you for Ian's thread

Thread by @IanCutress on Thread Reader App

@IanCutress: Sat in @ieee_isscc session 29: SRAM 1st paper: $TSM 38 Mb/mm2 N2 HD SRAM 2nd paper: $INTC 38 Mb/mm2 18A HD SRAM 3rd paper: @Mediatek 3nm TCAM 4th paper: @Synopsys 38 Mb/mm2 3nm HD SRAM...…

threadreaderapp.com

Went and found the ISSCC paper; RAM array raw cell size is indeed 0.021um2 for both Intel 18A and TSMC N2.

 

[siliconbruh999]

Went and found the ISSCC paper; RAM array raw cell size is indeed 0.021um2 for both Intel 18A and TSMC N2.

i just saw we have two Ian and both of the Ian's i were refering to were here .

 

[Daniel Nenni]

First 18A product, internal or external, is Panther Lake, ramping in 2H25. If anything it has been brought in - original projections were late 1H26 back when Pat first started. Then Clearwater Forest ramping in late 2H25 for 1Q26 launch. Turns out if you don't need to chase large dies without defects, stuff can get out the door sooner

So, Panther lake is the first ALL Intel 18A with BSPD? And Clearwater Forest is second generation? Or are there TSMC chiplets mixed in there?

Ramping means parts available to customers but not high volume manufacturing?

My understanding is that TSMC N2 will also be ramping in 2H 2025 and in HVM 1H 2026?

 

[kevin01]

So, Panther lake is the first ALL Intel 18A with BSPD? And Clearwater Forest is second generation? Or are there TSMC chiplets mixed in there?

Ramping means parts available to customers but not high volume manufacturing?

My understanding is that TSMC N2 will also be ramping in 2H 2025 and in HVM 1H 2026?

Clearwater Forest (a 288 e-core Xeon cpu product) should be all 18A. The challenge for CWF is that advanced packaging (Foveros direct or Foveros direct 3d) needs some further work, thus postponing to early 2026.

 

[Daniel Nenni]

Clearwater Forest (a 288 e-core Xeon cpu product) should be all 18A. The challenge for CWF is that advanced packaging (Foveros direct or Foveros direct 3d) needs some further work, thus postponing to early 2026.

That was my understanding as well but I can't keep track of all the clever names. More will be known about CWF next week. It looks like a great chip!

Whoever says Intel needs TSMC's help on 18A is in the wrong business.

 

[kevin01]

That was my understanding as well but I can't keep track of all the clever names. More will be known about CWF next week. It looks like a great chip!

Whoever says Intel needs TSMC's help on 18A is in the wrong business.

Advanced packaging appears poised to be a critical factor moving forward (it's already key for NVDA chips). I wish IFS all the best.

 

[Daniel Nenni]

Advanced packaging appears poised to be a critical factor moving forward (it's already key for NVDA chips). I wish IFS all the best.

I'm not a packaging expert but given that TSMC has big customer push I would bet on them. The TSMC Tech Symposiums have been all over packaging for the last few years. This year is no different:

https://www.tsmc.com/static/english/campaign/Symposium2025/index.htm

I hear Intel has great packaging technology but they really need customer engagements to keep up with TSMC, my opinion.

 

[blueone]

Turns out if you don't need to chase large dies without defects, stuff can get out the door sooner

Yeah, if your target markets can tolerate the concomitant increase in latencies and overall lower system-level performance. The move to chiplets so reminds me of years ago when data center systems vendors, and especially cloud computing companies, thought scale-out systems were the answer to their cost, performance, and scaling problems. It took time to get scale-out system-level designs right, especially fixing the inter-node networking performance issues, not to mention the basic distributed functionality strategies. Chiplet architectures may be a different animal in implementation, but challenges sure smell similar. (I know that odor.) I still think companies that can still get one big die designs out the door are going to keep kicking butt.

 

[lefty]

perhaps we should not judge an entire node based on a ISSCC paper. I am waiting to see what actually appears in products. thats just me LOL

Yeah, Intel 3 was meant to have better performance than TSMC N3 according to the white papers, but turned out to be worse than TSMC N4 when comparing actual products (Granite Rapids / Turin).

 

[chillfire]

Yeah, Intel 3 was meant to have better performance than TSMC N3 according to the white papers, but turned out to be worse than TSMC N4 when comparing actual products (Granite Rapids / Turin).

It is unfair to say Intel 3 is worse than TSMC N4 because of Granite Rapids / Turing comparison. Granite Rapids used last generation of architecture from redwood cove. Even the newer architecture Lion Cove on TSMC N3 lost to AMD's Zen 5 on TSMC N4. I think it is more of intel's design team issue rather intel's process node issue.

 

[MKWVentures]

That was my understanding as well but I can't keep track of all the clever names. More will be known about CWF next week. It looks like a great chip!

Whoever says Intel needs TSMC's help on 18A is in the wrong business.

Reminder: the Intel issue is financial, Not necessarily performance. And I wouldn't throw the 18A celebration party until it is in a real Product in real volume.... you might be surprised

Intel is currently shipping more Intel wafers at 7nm and above than Intel wafers < 7nm. This will be true throughout 2025.

 

[MKWVentures]

First 18A product, internal or external, is Panther Lake, ramping in 2H25. If anything it has been brought in - original projections were late 1H26 back when Pat first started. Then Clearwater Forest ramping in late 2H25 for 1Q26 launch. Turns out if you don't need to chase large dies without defects, stuff can get out the door sooner

I looked at 2021 Intel roadmaps. Panther lake was not a product. Panther Canyon was a product (cancelled). Panther cove was a core. and 18A was supposed to launch by June 2025 according to roadmaps. Nova lake was also 2025. The whole roadmap was redone a couple times. Where did you see a Panther lake in 2026?

18A/panther lake is not close to being launched so I wouldn't quite raise the "mission accomplished" Banner yet.

 

[OneEng]

Advanced packaging appears poised to be a critical factor moving forward (it's already key for NVDA chips). I wish IFS all the best.

I believe this is more of the current battle field than density increases in lithography processes. Intel's current Arrow Lake architecture suffers greatly from the ring bus latency. I am guessing those tile interconnects require some design changes in chip architecture as well as some pretty snazzy packaging engineering design to prevent issues in the computing pipeline.

Yeah, Intel 3 was meant to have better performance than TSMC N3 according to the white papers, but turned out to be worse than TSMC N4 when comparing actual products (Granite Rapids / Turin).

This is a very valid concern. I think lots of us have heard Intel over-promise, and then under deliver recently. The last one was the big "fix" coming to Arrow Lake.

Reminder: the Intel issue is financial, Not necessarily performance. And I wouldn't throw the 18A celebration party until it is in a real Product in real volume.... you might be surprised

Intel is currently shipping more Intel wafers at 7nm and above than Intel wafers < 7nm. This will be true throughout 2025.

... and this is the REAL problem for Intel.

It is my understanding that Intel has spent more on 18A development than a US Ford Class Aircraft Carrier. GAA and BSPDN requires significantly more passes / longer process time than all previous nodes by quite a bit..... meaning that the cost of each wafer produced is much higher.

I believe that the future of processor competition will reside in the domain of making a better processor for less money. I don't believe that the market exists that will allow CPU prices to increase from where they are ..... and certainly not to the extent of how much more the wafers cost!

Quite a sticky wicket.

 

[IanCutress]

I looked at 2021 Intel roadmaps. Panther lake was not a product. Panther Canyon was a product (cancelled). Panther cove was a core. and 18A was supposed to launch by June 2025 according to roadmaps. Nova lake was also 2025. The whole roadmap was redone a couple times. Where did you see a Panther lake in 2026?

18A/panther lake is not close to being launched so I wouldn't quite raise the "mission accomplished" Banner yet.

My own coverage of Intel and Intel's financials. Literally in the call and every conversation I've had with MJ and other execs.

@Daniel Nenni iirc they said 70% of the silicon of Panther Lake would be Intel. They might be including EMIB/packaging in that number.

from https://morethanmoore.substack.com/p/intel-2024-q4-financials

We're expecting Panther Lake to be commercial by end of year, CWF early in Q1. Ramp in this case really means 'achieved retail-class silicon', something like a B0 or B1 after the ES/QS cycles. Then it'll be put to the fabs, spend 3+ months before it's ready, and go to OEMs/retail.

 

[MKWVentures]

My own coverage of Intel and Intel's financials. Literally in the call and every conversation I've had with MJ and other execs.

@Daniel Nenni iirc they said 70% of the silicon of Panther Lake would be Intel. They might be including EMIB/packaging in that number.

View attachment 2820
from https://morethanmoore.substack.com/p/intel-2024-q4-financials

We're expecting Panther Lake to be commercial by end of year, CWF early in Q1. Ramp in this case really means 'achieved retail-class silicon', something like a B0 or B1 after the ES/QS cycles. Then it'll be put to the fabs, spend 3+ months before it's ready, and go to OEMs/retail.

Good info. thanks.

When do you think Intel will ship production Panther lake wafers from Fab 52?
When do you think the first external customer for 18A will ship production to an end customer?

 

[Daniel Nenni]

18A/panther lake is not close to being launched so I wouldn't quite raise the "mission accomplished" Banner yet.

Personally I would not raise the banner until 18A has big foundry customers. Making your own silicon work is very different from making customer silicon work.

 

[Daniel Nenni]

My own coverage of Intel and Intel's financials. Literally in the call and every conversation I've had with MJ and other execs.

@Daniel Nenni iirc they said 70% of the silicon of Panther Lake would be Intel. They might be including EMIB/packaging in that number.

View attachment 2820
from https://morethanmoore.substack.com/p/intel-2024-q4-financials

We're expecting Panther Lake to be commercial by end of year, CWF early in Q1. Ramp in this case really means 'achieved retail-class silicon', something like a B0 or B1 after the ES/QS cycles. Then it'll be put to the fabs, spend 3+ months before it's ready, and go to OEMs/retail.

ChatGPT said the same but I don't quite trust it yet:

Intel's upcoming Panther Lake processors are set to be manufactured predominantly using Intel's own 18A process technology. Specifically, approximately 70% of each Panther Lake processor will consist of Intel-produced silicon, with the remaining 30% likely sourced from TSMC. This approach aims to enhance Intel's profit margins by increasing in-house production.

Panther Lake is expected to launch in the second half of 2025, featuring up to 16 CPU cores and incorporating Intel's latest advancements in AI performance and power efficiency.

Intel's upcoming Clearwater Forest processors will utilize Intel's own silicon. These processors are designed with a disaggregated architecture, comprising multiple chiplets interconnected using advanced packaging technologies such as Foveros Direct 3D and EMIB 3.5D. The primary compute chiplets are manufactured using Intel's 18A process node, which incorporates the second-generation RibbonFET transistor architecture. This advancement is expected to deliver significant improvements in energy efficiency and performance over previous FinFET designs.

Originally slated for release in 2025, the Clearwater Forest processors have been delayed and are now expected to launch in the first half of 2026. This postponement is attributed to the niche market demand for E-core Xeon processors and the complexities associated with advanced packaging technologies.

 

[Xebec]

Yeah, if your target markets can tolerate the concomitant increase in latencies and overall lower system-level performance. The move to chiplets so reminds me of years ago when data center systems vendors, and especially cloud computing companies, thought scale-out systems were the answer to their cost, performance, and scaling problems. It took time to get scale-out system-level designs right, especially fixing the inter-node networking performance issues, not to mention the basic distributed functionality strategies. Chiplet architectures may be a different animal in implementation, but challenges sure smell similar. (I know that odor.) I still think companies that can still get one big die designs out the door are going to keep kicking butt.

Is it still a Chiplet if you tie together 2 or more "near reticle limit" dice?