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There's some quite interesting commentary over on SemiAccurate which is rather sympathetic to Pat Gelsinger (I can't get all the detail - not a subscriber). I'm not sure if Charlie is universally admired here, but I found his take on this interesting and possibly more insightful than most of the other stuff I've read so far on this.
There's some quite interesting commentary over on SemiAccurate which is rather sympathetic to Pat Gelsinger (I can't get all the detail - not a subscriber). I'm not sure if Charlie is universally admired here, but I found his take on this interesting and possibly more insightful than most of the other stuff I've read so far on this.
There's some quite interesting commentary over on SemiAccurate which is rather sympathetic to Pat Gelsinger (I can't get all the detail - not a subscriber). I'm not sure if Charlie is universally admired here, but I found his take on this interesting and possibly more insightful than most of the other stuff I've read so far on this.
I used to ask "Did someone at Intel kill Charlies's dog or something? He seems to have a vendetta" I am not sure how fair and balanced his commentary is LOL
FYI: I am a big fan of Zinsner, MJ, Naga, Kelleher as I think they are more pragmatic and open than Pat. We might get a more balanced report out on future soon (Maybe I am being too optimistic LOL).
I used to ask "Did someone at Intel kill Charlies's dog or something? He seems to have a vendetta" I am not sure how fair and balanced his commentary is LOL
That's the impression I'd always had. But not from the two recent pieces about Pat, which veer towards being strongly pro-Pat, not anti-today's Intel and only anti the Intel board (which seems fair comment to me).
His statement was something to the effect that after a large one time cost per FET reduction from process flow simplifications, cost per FET reductions in the EUV era have slowed down again. With High-NA replacing some multi-pass EUV steps as critical to getting a more normal cost per FET reduction (once again a one-time benefit).
This context is something I didn't realize - it looks like instead of "no cost scaling" to "something" it's more "less than usual scaling" to "better one-time" at least. Thanks!
For the 2024 SEMI International Strategy Symposium I was challenged by members of the organizing committee to look at where logic will be in ten years from a technology, economics, and sustainability perspective. The following is a discussion of my presentation. To understand logic, I believe it...
This is really interesting. Is that I/O drop around 14A the effect of High NA showing? And is it fair to assume that this incorporates impacts of BSPD around 2nm or 14A?
Rhetorically, I am interpreting this that for commodity products, the logic cost ahead looks pretty bleak. If it's 1.0x at N3, N2 is actually more costly per transistor (= that should indicate some will skip N2 as the performance gain of 10-15% at the same power won't justify higher sale prices on some products). After that, 14A looks pretty good vs. N3 (compounded performance gains *and* lower cost per transistors) though the SRAM regression might offset a good chunk of that. I guess this is all why we're seeing some chatter on Hyper NA now.
Last question - are these costs per transistor 'all up' - looking at the total cost of equipment+facility for a given fab node, or is it a little more focused on just the actual wafer steps, energy, etc? I assume the former.
This is really interesting. Is that I/O drop around 14A the effect of High NA showing? And is it fair to assume that this incorporates impacts of BSPD around 2nm or 14A?
The chart is a little weird. So the IO line is the cost per FET of a 16/14 "nm" class node with 11 metal layers. I would assume that drop is likely just wafer prices coming down. Some of the declines will be from different defect modes being squashed over time, and others might be as the buildings slowly deprecate over their 20+ year depreciatable lifetimes.
Rhetorically, I am interpreting this that for commodity products, the logic cost ahead looks pretty bleak. If it's 1.0x at N3, N2 is actually more costly per transistor (= that should indicate some will skip N2 as the performance gain of 10-15% at the same power won't justify higher sale prices on some products).
People said the same thing about 16FF since there was no shrink over 20nm. They were wrong because people greatly valued the enhanced electricals and the cost per FET was at least better than 28nm. I suspect TSMC N2 will do just fine. I don't think it will do as well as N3. But I say this because TSMC said they are cross qualifying N5 tooling to run N3, and with how similar the processes are. It looks like TSMC wants to migrate their customers to higher ASP N3E/P wafers over N5P/4P wafers. If it wasn't for N3 potentially absorbing some (or maybe eventually all) of the N5 business I think N2 would have the possibility of being a bigger node for TSMC than N3.
After that, 14A looks pretty good vs. N3 (compounded performance gains *and* lower cost per transistors) though the SRAM regression might offset a good chunk of that. I guess this is all why we're seeing some chatter on Hyper NA now.
Only thing that is kind of weird is CFET being a cost increase at first. The wafer cost adder will likely be very big, but unless logic makers reduce relax device sizes and packing density it is hard to imagine the CFET process density not increasing enough to make up for the cost adder.
Last question - are these costs per transistor 'all up' - looking at the total cost of equipment+facility for a given fab node, or is it a little more focused on just the actual wafer steps, energy, etc? I assume the former.
No Scotten, is using techinsight's wafer cost model (i.e. what it costs TSMC to make that wafer they sell for whatever price they are selling it for). Makes sense to do it that way to me since wafer margins change over time with utilization and if you are looking say TSMC vs TSMC their added margins are likely similar across processes (of course with the exception of brand new process nodes where their wafers have much lower than corporate average GMs).
That suggests differences over the quality of PG's execution of the plan. To repeat, PG massively screwed up the expectations game for everyone, and this is something most any board can sink their teeth into.
While my primary metric for Intel's likely success was PG or now his successor firing swaths of infighting middle and higher managers and making it clear that culture was going to be punished severely, which you might be able to read in Lip-Bu Tan's parting from the board remarks months ago, I was always worried he wasn't a process guy.
Zinsner is "guessing" the next CEO will have "foundry experience". Which is not necessarily the same thing, speaks to a need to do better with outside would be customers, but is certainly downstream of processes the customers would want.
The one thing that Pat definitely screwed up recently was the financial forecasting. Repeated huge misses vs forecasts without any warning. May not have been Pat's fault directly, but he let it happen. Hard to see how Zinsner wasn't equally responsible here though.
Maybe it's all about pacifying Wall Street and not the tech or product stuff at all ?
Investors and debtors aren't the only ones worrying if Intel runs out of money before it can right itself. It would be inconvenient if you had to be the highest bidder for a batch of your chips or wafers in a Chapter 7 liquidation auction.
The one thing that Pat definitely screwed up recently was the financial forecasting. Repeated huge misses vs forecasts without any warning. May not have been Pat's fault directly, but he let it happen. Hard to see how Zinsner wasn't equally responsible here though.
Maybe it's all about pacifying Wall Street and not the tech or product stuff at all ?
With Intel insisting the plan remains in place the only thing I can come up with is a disagreement about how fast Gelsinger was investing in capacity. I expect to see Intel slow down spending on filling their fabs with tool. I expect that to show up in when they start moving tooling into the Ohio fabs (and maybe both) as there is a need to bring up at least one of the new AZ fabs before the end of 2025 to ramp 18A.
True… they would have basically 100% knowledge of their impending Q4 numbers and maybe it’s a blood bath (e.g. below the already low expectations). The board getting out ahead of yet another disaster could be the overall explanation.
I don’t really know if that’s the right move to replace Pat because of that, but certainly I can see why a board would make this move after repeated disastrous quarters in order to assuage the market.
I think Pat is a good leader, but I also think he came in with hubris and had the wrong strategy. I have always maintained that the only viable path forward for Intel is to split the foundry and design businesses, and Pat was committed to keeping them together. He did as good a job as could be expected all things given, but you can't fix a fundamentally wrong strategy.
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