Gelsinger “retires”

[kevin01]

I do think that the plan is clear now, they are seeing good signal in 18A and maybe future generations of product. Pat is good as a vision, but he's probably the worst in managing client and investor expectation and confidence. The board need someone who can sell the story. Hence Pat is out.

One thing is clear, the board wanted to shore up investor confidence, but now, judged by the market reaction, they get the opposite. They need to provide a clear explanation to why PG was removed, and fast.

The INTC board should retire.

 

[MKWVentures]

I do think that the plan is clear now, they are seeing good signal in 18A and maybe future generations of product. Pat is good as a vision, but he's probably the worst in managing client and investor expectation and confidence. The board need someone who can sell the story. Hence Pat is out.

I am not sure the board saw that LOL. We will know soon enough.

 

[MKWVentures]

One thing is clear, the board wanted to shore up investor confidence, but now, judged by the market reaction, they get the opposite. They need to provide a clear explanation to why PG was removed, and fast.

The INTC board should retire.

Every Financial indicator is dangerously worse now than when he took over. All competitors have had wildly growing finances.

 

[kevin01]

Every Financial indicator is dangerously worse now than when he took over. All competitors have had wildly growing finances.

Semiconductor business has very long cause-and-effect cycles.

 

[soAsian]

Pat Gelsinger on LinkedIn: Leading Intel Corporation has been the honor of my lifetime. I am forever… | 862 comments

Leading Intel Corporation has been the honor of my lifetime. I am forever grateful for the many colleagues around the world who I have worked with as part of… | 862 comments on LinkedIn

www.linkedin.com

"Leading Intel Corporation has been the honor of my lifetime. I am forever grateful for the many colleagues around the world who I have worked with as part of the Intel family and can look back with pride at all that we have accomplished together. Thank you all!"

 

[Xebec]

So, if


then TSMC is doomed?

Long term - fabrication is a race to the bottom.

If TSMC ends up being the 'sole survivor' and ends up generations ahead of everyone else -- they may still be able to command high margins when node scaling halts or becomes 1-2% a year.

but if others keep up the competition, OR if innovation keeps yielding small(er) improvements -- it's possible further investments will not be justified at some point (as long as TSMC is publicly held).

It's a really long tail of course..

 

[count]

So, if


then TSMC is doomed?

Personally, I think it means China has a legit chance of catching up if Moores law is slowing down.

 

[kevin01]

Personally, I think it means China has a legit chance of catching up if Moores law is slowing down.

Then everybody in the semi will be fxxked. Just look at the automobile industry now -- look at VW, Nissan, etc.

 

[lispwright]

For years, people have been talking about the downfall of Moore's Law. Everyone has assumed that the cause of this downfall would be physics or some other technical problem when in fact Moore's Law is dead because of financial issues.

Quoting Moore in 1965:

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year.

And I believe in the period where it roughly held up, it was more about "financial issues" than technical, as long as the technical could keep up with what made economic sense.

Now the technology has gotten so demanding, see for example ASML's EUV machines plus the issues of hitting wafers with much higher energy photons, it's stacking crazy on top of crazy, it's a miracle it works at all. And only 3 logic companies are even trying to keep up.

A second miracle is that there's one semiconductor user who's profit margins and sales forecasts are so high and reliable it can pay for cutting edge logic node development. I suppose that means Apple+TSMC replaced Intel.

I believe that the industry in general will be effected by this new reality. For the past .... well forever (since IC's became a thing), the semi industry has primarily relied on having 50% more transistor budget for each new design. Such huge improvements in process drove the huge improvements in performance.

In this 1965 observation looking back at least 5 years for the history of monolithic ICs, to today, Dennard scaling coined in 1975 was a long term, 37 year thing out of the 64 years so far of ICs. Before and after we had to squeeze performance mostly out of the "width" of CPUs, which were mostly CISC.

In addition to the massive change in fortunes for Moore's Law, the grip of x86 on it's markets is coming to an end. There is certainly nothing inherent in x86 designs that make them superior to RISC designs and in fact, x86 chips have been mostly RISC for quite some time in order to have ILP (with equal length data and instructions).

RISC designs greatly benefited from low required all on one chip transistor budgets and a period of relatively high memory to logic speeds. The former was an extreme premium until CISC CPUs could fit on a chip. See for example DEC stumbling hard with the VAX because the company was run by SSI to LSI veterans who didn't appreciate VLSI. I also saw this pattern in Lisp Machine history.

Today the latency especially gap between logic including SRAM caches on a single chip and offboard DRAM is very high, and I've read x86 significantly benefits from compact instruction encoding due to its cache-ability. This was not a so much of a design goal of early RISC macro-architectures. As an extreme example, see their delay slots after branch instructions, whatever their demerits after branch prediction became big, they are also a code compaction penalty. See also ARM and RISC-V compact code instruction sets.

I see some direct evidence of this in Intel performance cores which increased only the L1 data cache to 48KiB with Sunny Cove in 2019 after 13 years of a balanced 32KiB each instruction and data (that is, it implies more pressure on that cache). I'm not hardly as familiar with Atom and efficiency core cache history, but I see some similar patterns.

 

[count]

Then everybody in the semi will be fxxked. Just look at the automobile industry now -- look at VW, Nissan, etc.

Foundry, maybe. The fabless companies like Nvidia, AMD, MediaTek, will all continue to grow and innovate

 

[nghanayem]

*AMD and Intel have largely given up on sub $150 processors, and Nvidia and AMD are trying not to sell GPUs below ~ $300 and $200 respectively. Nvidia's CEO has made a lot of comments about Moore's Law being dead and transistor costs going up since around the 20nm era. Chiplets have pushed this problem back some years but you can only do so much with packaging to defer this problem.

I've said it before, and I will say it again. Jensen is full of baloney on this. Even a process that is comically overcomplicated for its density like intel 7 has a better cost per FET than intel 14nm (albeit not better than a usual full node of scaling like intel guided back in the 2010s if one looks at the updated chat in Intel's new segment reporting presentation). Intel 22nm was also a normal cost per FET imorovement over their 32nm even with the insertion of finFET and self aligned contacts. This claim that TSMC 20nm was more expensive than 28nm was never a fair comparison because it was at then current 28nm yields and wafer prices (ie significantly discounted from the year 0 pricing) versus TSMC 20nm yields and prices back when TSMC was in 20nm risk production. The real reason for 20nm's failure was almost certainly not the cost per FET. 20nm wasn't finFET so the performance-power improvements over 28nm were almost non-existent. When you have 16FF coming one year later with the same density, a bit higher wafer costs, and WAY better electricals; it made 0 sense for most of TSMC's customers to waste time and money investing into a process that was stillborn. Doubly so when Samsung was at the time already launching finFET products to market with 14LPE Exynos chips. If you adjust cost to the same point in time, even N3E which many armchair "experts" decry as "not worth it over N4" must have a reasonably meaty cost per FET reduction. TSMC claims a full chip density boost of 1.3x. When you look at teardowns of N3E vs N5, I literally can't imagine any way for N3E to be more than a 30% wafer cost adder. A good heuristic is every new logic process tech being around a 15% wafer cost adder (of course, some are higher and some are lower). Given how only a couple of new metal layers layers shrunk small enough to need a swap to SALELE, the MEOL being very similar, and the FEOL is also very similar. I wouldn't be shocked if the cost adder was 10% or less. Now, granted TSMC's margins are higher than they were 10 years ago, but when I look at how NVIDIA's gaming and datacenter GPU segments have their margins go up every year as the ASPs go up. Color me skeptical that cost per transistor is actually up.

Techinsights' Dan H. did a look at TSMC cost per FET (late last year I think). They've come to basically the same conclusion, and their wafer prices/cost models have wafers sitting far far far lower than the numbers often bandied in the media for what TSMC's wafer prices are. Since I am not going to just copy and paste their results here, out of respect for their work and my selfish desire to not dig through and find the article. Here is an example of intel's cost to produce three generations of intel CPU with the charts aligned to have time = 0 be the quarter after the products launched. Note that Haswell is the successor to Ivy bridge with enhanced GPU/IOs and better optimization around the new finFET transistors (since Ivy bridge is a slightly enhanced die shrink of a 32nm design), and Broadwell is an enhanced die shrink of Haswell. Notice how rapidly cost for Ivy and Broadwell dropped as production ramped and yield increased. Lead products on new process nodes always look similar to this. After their first years of production, you can see that Broadwell is cheaper than Ivy bridge despite Broadwell having a larger Xtor budget. Also notice how the more complex Haswell started right inline with where Ivy ended the year (both are on 22nm with only a 2Q offset in real time). Over the first year of production, Broadwell would even mature to be cheaper to produce than its 22nm sibling which. Haswell even has the advantage of enjoying 2 years of yield enhancements and cost reductions compared to Broadwell which started off behind Ivy Bridge on yield and had to spend its first year catching up. I'm sure this chart looks even better for TSMC as their 10FF is a decent chunk denser than i14nm and likely isn't much more expensive than intel's 14nm.

Now is the cost per transistor trend in 2024 declining like it was in the 2000s? No, absolutely not. But I will die on the hill that cost per transistor did NOT hit its lowest in 2012 with TSMC 28nm. Nor do I accept the notion that cost per transistor has stagnated around 28nm values. I have never seen credible evidence to support it, and the only people who claim that are fabless firms justifying why they "needed" to raise their prices.

 

[Xebec]

I've said it before, and I will say it again. Jensen is full of baloney on this. E

Now is the cost per transistor trend in 2024 declining like it was in the 2000s? No, absolutely not. But I will die on the hill that cost per transistor did NOT hit its lowest in 2012 with TSMC 28nm. Nor do I accept the notion that cost per transistor has stagnated around 28nm values. I have never seen credible evidence to support it, and the only people who claim that are fabless firms justifying why they "needed" to raise their prices.

My comment was more focused on that the writing is on the wall that the scaling trend isn't favorable for cost per transistor, and eventually it won't be worth buying the next node for even more product segments than it is today. (I wish we had a Y access for that 14nm vs 22nm Intel comparison, that could be a 5% reduction or a 30% reduction ).

I'm also not saying Jensen was necessarily "right" on his 20nm comments, but for him to make public comments - he's clearly not happy with what's going on with costs for future nodes. Pat G (who I know everyone here loves) also made comments about High NA being needed to resume cost scaling at the transistor level. There's at least smoke in this area.

That said, is there any published or public data showing the cost per transistor difference of N3 vs N4/N5, (and with a comparison to N7 costs)? (And does that include the full set costs -- from design through production, and the cost of the fab not just the run rate per wafer).

 

[Barnsley]

That would be a good plan..... IF demand picks up for foundry, then expand further (But they made all these wild commitments)

First impression I get from people (sometimes these are wrong) Is that the Intel board wants to spin off IFS faster. I do know there are proposals that have been on the table for years.... and they are still discussing these. This is the only way to have clarity going forward without Pat IMO. A subsidiary doesn't fix the stock price anytime soon.... It needs to be off the books.

I think the ex IBM guys at intel have experience when giving up and ending the IDM plan. How it works ownership wise could be anything.

Products or Foundry ... the "let's do both!!!" crowd is getting smaller (which is good)

Its interesting that there seems to be no value in maanufacturing the end product.

Which ultimately determines whether these fantastical designs will come into existence.

Doesnt that imply the system is broken?

 

[hasty2333]

Then everybody in the semi will be fxxked. Just look at the automobile industry now -- look at VW, Nissan, etc.

I don't think they'll catch up that easily. In the worst case, I doubt it's even possible. Chip manufacturing is a highly complex and resource-intensive process. Given their current situation, they'll need a lot more talent to break the restriction. China is good at following, but creation? We'll see.

 

[Barnsley]

Foundry, maybe. The fabless companies like Nvidia, AMD, MediaTek, will all continue to grow and innovate

Who is doing the manufacturing?

If its not economically viable to manufacture who is going to do it?

 

[Daniel Nenni]

From LinkedIn:


Bob Grim
Yesterday was an exciting day for us at Tenstorrent... I would rather have not shared the headlines with Pat Gelsinger's retirement news, but it is what is and we got plenty of coverage for our big funding announcement.

As most you know, I spent two years at Intel Corporation and was there when Pat took over as CEO. I have posted thoughts here about Intel, and now they face another challenge - who to steer the ship? There is a lot of speculation out there about this, but here are 6 people that I think are being considered for the role. Four of them are commonly mentioned online as potential replacements, but I don't think you can leave Gregory Bryant and Jack Huynh out of the conversation either.

- Lip-Bu Tan is clearly the internet favorite to replace Pat and he obviously has the pedigree for it and clearly journalists would like us to consider him the front runner. Does he want to do the job though?

- Raja Koduri is also listed as a potential replacement. Might he be interested? Who knows... he definitely knows a lot of the business there and there aren't many folks like him. I just think he has other projects in his heart. If I am right then its too bad - his knowledge of product might really help Intel.

- Greg Lavender is an obvious choice and commonly mentioned online as a candidate. His knowledge of the company and how it works could be invaluable. I don't think it will be him though... otherwise he would have been part of the interim CEO group.

- Diane Bryant is the candidate that wouldn't surprise me if she got the job. I do not know Diane, but I hear nothing but good things and her track record of success is impeccable. She knows product and her years of experience at Intel will be a great help (as would her experience after leaving Intel). I think she has a real shot if she wants it.

- Gregory Bryant, or GB as most of us know him as, is a super interesting candidate. He knows what it takes to build a successful silicon business and if he can find a partner in crime to really drive better silicon products with him then he would be a compelling candidate to come back and take the helm. There aren't many people with his experience of driving a P&L of nearly $40B.

- Ok... admittedly Jack Huynh is a flier... but every good list needs one. If you don't know Jack, then you don't know that he has been behind most good business decisions at AMD for decades. While he can't take credit for driving the Zen architecture... he is responsible for driving and crafting deals and businesses at AMD that have saved the company on multiple occasions. Those of us in the know wonder if he is on Lisa Su's short list for her succession planning.

I know people wonder why I don't add Jim Keller to this list... its primarily because I believe he wants to stay at Tenstorrent.

Ok - the list is made - the gauntlet thrown. Talk amongst yourselves... who takes over for Pat?

 

[nghanayem]

My comment was more focused on that the writing is on the wall that the scaling trend isn't favorable for cost per transistor, and eventually it won't be worth buying the next node for even more product segments than it is today. (I wish we had a Y access for that 14nm vs 22nm Intel comparison, that could be a 5% reduction or a 30% reduction ).

Your good Xebec, I wasn't calling you out and I know it is OT. I just see statements like that quoted all the time and wanted to nip it in the bud. Fab engineer who works at 28nm and below fabs could tell you it just isn't true. Densities have simply increased faster than the cost adder. Only exception I can think of is TSMC 16FF and GF 14LP. Both processes have a very minor density uplift while moving to finFET. So not exactly a surprise that 16FF and 14LP cost per FET is greater than their 22/20nm processes in a like for like comparison.

I'm also not saying Jensen was necessarily "right" on his 20nm comments, but for him to make public comments - he's clearly not happy with what's going on with costs for future nodes.

Well, we all like things cheaper; don't we? And he was around long enough for the days of 2x density with 15% cost adders and 20+% PPW uplifts rather than the current status quo of 1.3x for 15% with a sub 20% PPW uplift (and if we are comparing to the latest TSMC subnode rather than the initial version then sub 10% PPW uplifts).

Pat G (who I know everyone here loves) also made comments about High NA being needed to resume cost scaling at the transistor level. There's at least smoke in this area.

His statement was something to the effect that after a large one time cost per FET reduction from process flow simplifications, cost per FET reductions in the EUV era have slowed down again. With High-NA replacing some multi-pass EUV steps as critical to getting a more normal cost per FET reduction (once again a one-time benefit).

Side note: I really don't like that this chart is a spline and not a scatter plot. It kind of makes it look like there was a significant cost per FET reduction from the 14nm pluses and 10nm SF -> intel 7 rather than those enhancements mostly coming from 10nm and intel 4. Which is not to discount continuous improvement from yield and cost reduction opportunities (they are very important), but from a raw process structural cost perspective it is all about mask layers, tool numbers, tool costs, and areal density.

That said, is there any published or public data showing the cost per transistor difference of N3 vs N4/N5,

Is TSMC N3E a Major Redesign or just a Variant? - First Observations of Differences | TechInsights

TechInsights has torn down the recently released Apple iPad Pro 11-inch featuring Apple M4 SoC die, with markings TMRV93.

www.techinsights.com

Introducing TSMC N3E As Seen In Apple M4 SoC | TechInsights

TechInsights shares preliminary results of the Apple M4 analysis on design blocks like GPU and CPU, featuring 2-1 finFLEX and 3-2 finFLEX libraries, respectively. Dive into our on-going analysis and discover the measurements of critical dimensions of TSMC’s 3nm 2nd generation process node: the...

www.techinsights.com

Introducing TSMC N3E: The Power Behind Apple's M4 SoC | TechInsights

In a recent teardown of the Apple iPad Pro 11-inch, TechInsights revealed details of Apple's latest silicon: the Apple M4 SoC, codenamed TMRV93, built on TSMC's advanced N3E process. This surprise release demonstrates Apple's agility in adopting cutting-edge semiconductor technologies ahead of...

www.techinsights.com

Techinsights has some complementary reports on N3E

Scotten also did a write-up on the topic:

ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability - Semiwiki

For the 2024 SEMI International Strategy Symposium I was challenged by members of the organizing committee to look at where logic will be in ten years from a technology, economics, and sustainability perspective. The following is a discussion of my presentation. To understand logic, I believe it...

semiwiki.com

(and with a comparison to N7 costs)?

Per TSMC:

Per nghanayem: kind of hard for me to guesstimate exactly how N7 and N5 compare because even though total layer count is down each EUV mask layers tend to have more non litho scanner operations than an equivlent ArF/KrF mask layer. The scanners are also more expensive per exposure too. Since a minority of the total layers have any reason to be EUV on N5, I can't imagine any world where the wafer cost adder is greater than the like 1.5-1.7x full chip density boost.

(And does that include the full set costs -- from design through production, and the cost of the fab not just the run rate per wafer).

Design and mask set costs are hardly relevant to cost per FET. By cost per FET I am mostly talking about wafer cost (not price) out of a fab in a like for like scenario (ie same yield, scale, cost of fab inputs, utilization, no deprecation, etc) divided by the number of Xtors on a wafer with a given product i.e. structural cost.

 

[blueone]

From LinkedIn:

I saw this post on LinkedIn. Comments below.

Bob Grim
Yesterday was an exciting day for us at Tenstorrent... I would rather have not shared the headlines with Pat Gelsinger's retirement news, but it is what is and we got plenty of coverage for our big funding announcement.

As most you know, I spent two years at Intel Corporation and was there when Pat took over as CEO. I have posted thoughts here about Intel, and now they face another challenge - who to steer the ship? There is a lot of speculation out there about this, but here are 6 people that I think are being considered for the role. Four of them are commonly mentioned online as potential replacements, but I don't think you can leave Gregory Bryant and Jack Huynh out of the conversation either.

- Lip-Bu Tan is clearly the internet favorite to replace Pat and he obviously has the pedigree for it and clearly journalists would like us to consider him the front runner. Does he want to do the job though?

I agree with, Dan, too distracted, and ran a software company for about a decade, however connected it is to chip design.

- Raja Koduri is also listed as a potential replacement. Might he be interested? Who knows... he definitely knows a lot of the business there and there aren't many folks like him. I just think he has other projects in his heart. If I am right then its too bad - his knowledge of product might really help Intel.

Don't know him, but difficult to see him in this role, considering manufacturing.

- Greg Lavender is an obvious choice and commonly mentioned online as a candidate. His knowledge of the company and how it works could be invaluable. I don't think it will be him though... otherwise he would have been part of the interim CEO group.

A software guy. Never done hardware design, never done manufacturing. Being senior and watching isn't doing.

- Diane Bryant is the candidate that wouldn't surprise me if she got the job. I do not know Diane, but I hear nothing but good things and her track record of success is impeccable. She knows product and her years of experience at Intel will be a great help (as would her experience after leaving Intel). I think she has a real shot if she wants it.

I know Diane, I don't think she'd be a good choice. Risk averse. Note that Bryant and Diane Greene got fired for lack of results at Google Cloud. Not a good sign.

- Gregory Bryant, or GB as most of us know him as, is a super interesting candidate. He knows what it takes to build a successful silicon business and if he can find a partner in crime to really drive better silicon products with him then he would be a compelling candidate to come back and take the helm. There aren't many people with his experience of driving a P&L of nearly $40B.

A definite maybe. I don't know Gregory. The only one on this list that sounds passable and has a fairly decent background.

- Ok... admittedly Jack Huynh is a flier... but every good list needs one. If you don't know Jack, then you don't know that he has been behind most good business decisions at AMD for decades. While he can't take credit for driving the Zen architecture... he is responsible for driving and crafting deals and businesses at AMD that have saved the company on multiple occasions. Those of us in the know wonder if he is on Lisa Su's short list for her succession planning.

I know people wonder why I don't add Jim Keller to this list... its primarily because I believe he wants to stay at Tenstorrent.

Keller might make a good CTO for the design side, if he was interested, which I'd bet he's not.

 

[OneEng]

So, if


then TSMC is doomed?

Interesting question, but no. I don't think so.

TSMC will remain competitive through having the best Fab processes at the best price that can be obtained. They will be able to do this through careful management of costs and by spreading the crazy high NRE for new nodes across more customers than others have. TSMC also has an integrated strategy for equipment that is no longer leading edge. These older process technology equipment lines are long paid for and can be used to create revenue that supplements the business. TSMC also has a very mature set of on-boarding tools to efficiently bring on new customers and new designs. These tools are manufacturing hardened over several generations of continuous improvement.

Intel has, until now, considered their process technology a means to an ends for their CPU business. IMHO, changing over to a foundry service will require much more than saying so and talking to a few potential customers about the foundry and a single node of 18A.

Regardless, all fabs will have to deal with the diminishing returns of new node processes and the exponentially increasing costs to produce them. In my mind, this means that new nodes will be further and further apart in time in the future with more "tweaks" in-between. More time and effort will be placed on cost efficiency as well. While we may some day be able to technically produce a chip with a 100 layer stack up, we will likely never be able to afford to make it.

 

[OneEng]

Now the technology has gotten so demanding, see for example ASML's EUV machines plus the issues of hitting wafers with much higher energy photons, it's stacking crazy on top of crazy, it's a miracle it works at all. And only 3 logic companies are even trying to keep up.

LMAO. I have never heard it put that way before, but I agree.