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A tale of three CFETs

N

nghanayem

Well-known member
At IEDM23 we got to get a glimpse at the early enabling work for the big three’s CFET technology. One thing I found very interesting was the seemingly different research priorities.

Samsung in someways had simultaneously the most and least impressive showing. They showed off a CFET device with tighter cpp than even N3B. But unfortunately they lacked the extra sauce to go with it (at least based on the synopsis listed below as I haven’t yet gotten the chance to read Samsung’s full paper). As far as I know this is also the first time Samsung has showed off real CFET devices.

TSMC for their part wasn’t very far behind on poly pitch with 48pp cells that are likely similar to what we will see on N3E. They also had a nifty dielectric isolation that feels reminiscent of forksheet FET as well as N3B’s gate endcap. I am not sure how you would go about doing devices with merged gates without using another litho and epi pass so that lower Ge content SiGe gets deped for the cells that want a common gate. Either way it gets two thumbs up from me as I am actually quite fond of the concept behind forksheet FETs.

Not to be left out intel has also updated us on their developments. In this work they were keeping the poly pitch very loose at 60nm. However they extended their 2 sheets lead to a 3 sheet lead vs everyone else’s CFETs. Unsurprisingly intel has also made sure to market their lead in BSPD and even showcased fully integrated circuits (specifically inverters). Besides the obvious gate shrinkage, one area of improvement seemed to be doing the enabling work for more complex circuitry.

All told very interesting that Samsung is prioritizing getting the device down to production like pitches. TSMC has a similar focus with a greater focus on yield as their dielectric wall should greatly help with GtG shorts. Intel for its part seems to be focusing on creating a transistor architecture that is ready for the prime time and then shrinking from there.

spectrum.ieee.org

Intel, Samsung, and TSMC Demo 3D-Stacked Transistors

The Big Three can now all make CFETs—next stop on the Moore’s Law roadmap
spectrum.ieee.org spectrum.ieee.org
 
I was at IEDM and my impression of 2nm is that TSMC, Samsung, and Intel are still on the same path as 3nm. Intel will have the highest performance, TSMC will have the highest density and lowest power and highest yield. Samsung is harder to read. This is their second version of GAA, the first did not yield and was not competitive with TSMC N3. This new version does look to be more production focused, which is great, but I don't think it will be competitive on PPA with Intel and TSMC, my opinion.

I had thought the big TSMC customers would stick with N3 for an extra generation before jumping to TSMC N2, Intel 18A, or Samsung 2nm. Well I was wrong. Word on the street is that TSMC N2 will have the majority of N2 design starts next year, not unlike TSMC N3, but not ALL of the design starts like TSMC did at N3. I found some Intel 14A and Samsung 2nm design starts much to my surprise.

Bottom line: It looks like we have a three horse race again!
 
Last edited:
Daniel Nenni said:
I was at IEDM and my impression of 2nm is that TSMC, Samsung, and Intel are still on the same path as 3nm. Intel will have the highest performance, TSMC will have the highest density and lowest power and highest yield. Samsung is harder to read. This is their second version of GAA, the first did not yield and was not competitive with TSMC N3. This new version does look to be more production focused, which is great, but I don't think it will be competitive on PPA with Intel and TSMC, my opinion.

I had thought the big TSMC customers would stick with N3 for an extra generation before jumping to TSMC N2, Intel 14A, or Samsung 2nm. Well I was wrong. Word on the street is that TSMC N2 will have the majority of N2 design starts next year, not unlike TSMC N3, but not ALL of the design starts like TSMC did at N3. I found some Intel 14A and Samsung 2nm design starts much to my surprise.

Bottom line: It looks like we have a three horse race again!
Click to expand...
Kind of surprised intel is already showing off intel 14A to external (assuming that is the name they go with).
 
nghanayem said:
Samsung in someways had simultaneously the most and least impressive showing. They showed off a CFET device with tighter cpp than even N3B. But unfortunately they lacked the extra sauce to go with it (at least based on the synopsis listed below as I haven’t yet gotten the chance to read Samsung’s full paper). As far as I know this is also the first time Samsung has showed off real CFET devices.
Click to expand...
It still looks like no one has broken through 45nm CGP, which was already shown on TSMC N3 FinFET.
 
"I think everybody is looking at the transistor of TSMC’s N2 versus our 18A," said Gelsinger. "It is not clear that one is dramatically better than the other. We will see who is best. But the backside power delivery, everybody says Intel, score. You are years ahead of the competition. That is powerful. That is meaningful. It gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance."

I wonder if TSMC will release N2 chiplets before Apple releases the N2 SoC? Other wise it will not be a fair comparison since it will be years before Intel releases a complex SoC on 18A with back side power delivery.
 
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