Bridging the Gap between Foundry and IC Design at #53DAC

In our semiconductor ecosystem we often specialize the engineers and therefore EDA tools into separate silos like Foundry, front-end design, back-end design, tapeout, etc. What I discovered at #53DAC a few weeks ago was that some EDA companies actually bridge the gap between foundry engineers and IC designers with their tools. Proplus Design Solutions is one such company and I had the pleasure to talk with Lianfeng Yang about this.

Q: What’s new with Proplus in this past year?

We have a new tool called Model Explorer Pro (MEPro), and it bridges the gap between circuit design, CAD and process development. For example each process node undergoes several version changes in the PDK based upon changes to the design book. Our new tool automates this process of changes to the PDK, instead of relying upon just a printed design book. It’s a visualization tool based on a database summary of that process, where you can quickly browse the process strengths and weaknesses. New versions of PDK are created and compared more easilty.

inside the foundry it’s useful for QA control of PDK updates, allows designers to understand and benchmark processes between companies, and see the metrics of the devices (IV, leakage, LDE, built-in circuit analysis). You can compare two processes between a foundry or even to an automated comparison between processes (28nm High speed vs low power) in just minutes.

Q: Where does the software engineering happen at Proplus?

We have engineering in San Jose, CA, Beijing and Jinan China.

Q: What operating systems does your software support?

Our supported operating systems are Linux and Windows.

Q: Which EDA tool are you best known for?

That would be our BSIMProPlus tool, a Windows based product for device engineers.

Q: What makes MEPro so special?

With MEPro it’s creating an entirely new product category, so there aren’t even any competitors yet.

Q: What can you tell me about your SPICE circuit simulator?

We have a parallel SPICE simulator called NanoSpice which offers a faster turn around time, is more efficient, and has sufficient accuracy for RF down to digital. We have FinFET customers like Silicon Creations using NanoSpice on both 10nm and 7nm designs, and the tool has a capacity for large analog chips. eSilicon is another customer and we have about 10 customers that have publicly endorsed the tool.

Q: What are the core competences at Proplus?

Primarily we are device modeling experts with a deep knowledge of how FinFET, FDSOI, BSIM4 (Berkeley graduates) and CMG models (growing parameters) work.

Q: Do you have a circuit simulator for memory designers to use?

Yes, it’s called NanoSpice Giga and has been with customers for over one year now, used by the memory market and IDMs.

Also read other Pro Plus Articles