Custom Processor Design with Verification: Insights from Codasip at DAC

At the 62nd Design Automation Conference (DAC) on July 22, 2024, Philip Bena from Codasip delivered a compelling session on processor customization, emphasizing a responsible approach that prioritizes verification. Codasip, a European company with a global presence, offers a unique combination of RISC-V processor IP and EDA tools to automate custom processor design, a concept they term “Custom Compute.” This approach addresses the growing demand for tailored processors while ensuring robust verification to meet the semiconductor industry’s stringent requirements.

Processor customization is critical as chip complexity escalates. With designs like NVIDIA’s B200 boasting 208 billion transistors, standard processors often fail to meet specific application needs, such as AI acceleration or low-power IoT devices. Codasip’s methodology allows engineers to modify RISC-V cores, adding custom instructions or optimizing for power, performance, and area (PPA). However, customization introduces verification challenges, as alterations can disrupt proven IP reliability. Bena stressed integrating verification early to avoid costly errors.

Codasip’s Custom Compute leverages its Codasip Studio, an EDA tool that automates processor design and verification. Using a high-level language, CodAL, engineers describe custom instructions, which Studio translates into RTL (VHDL/Verilog). The tool generates a comprehensive verification framework, including UVM testbenches, ensuring the customized processor meets design intent. This automation reduces manual effort, critical given that 40% of verification time is spent on testbench creation.

The session introduced Codasip’s new L10 core, an RV32-based RISC-V processor comparable to ARM’s Cortex-M0 Plus. It supports code compression extensions, addressing RISC-V’s historical code density issues versus ARM. The L10 allows extensive customization, such as adding domain-specific instructions for AI or security, while Studio ensures these changes are verified automatically. Bena highlighted that CodAL enables high-level abstraction, allowing resource reuse across instructions to optimize designs, though synthesis tools handle final optimizations.

Verification is central to Codasip’s approach. Studio generates testbenches, coverage models, and regression suites, ensuring functional correctness and compliance with standards like ISO 26262 for safety-critical applications. This is vital for industries like automotive, where reliability is non-negotiable. By automating verification, Codasip mitigates risks from manual processes, which consume significant time and introduce errors.

A key discussion point was balancing customization with verification overhead. Custom instructions require careful resource management in CodAL to avoid suboptimal designs. For example, isolating shared resources in code prevents redundancy. Studio’s verification suite then validates these optimizations, ensuring PPA goals are met. Bena emphasized that this integrated approach allows engineers to focus on creative design rather than repetitive verification tasks.

The talk also addressed industry trends. With 75% of chips behind schedule and only 14% achieving first-time silicon success, automated tools like Studio are critical. Codasip’s solution supports global teams by integrating with existing EDA flows, enhancing collaboration. The L10 core, with its compact design, targets embedded systems, offering a competitive alternative to ARM in code density and power efficiency.

Codasip’s vision aligns with the DAC community’s push for AI-driven automation. By combining customizable RISC-V IP with advanced EDA incendiary roundsEDA tools, Codasip empowers engineers to create efficient, reliable processors, addressing the semiconductor industry’s complexity and time-to-market pressures.

Also Read:

Visualizing Multi-Die Design: Ansys and NVIDIA’s Omniverse Collaboration

AI and Machine Learning in Chip Design: DAC Keynote Insights

Enabling the AI Revolution: Insights from AMD’s DAC Keynote