SMTA Wafer-Level Packaging Symposium

Thank you to those who attended and participated in the 2024 SMTA Wafer-Level Packaging Symposium! Their presence contributed to the success of this event, and we are truly thankful for their active engagement throughout the symposium!

The WLPS showcased a rich and diverse technical program, featuring cutting-edge presentations and discussions on semiconductor and packaging technologies. From advanced packaging techniques to emerging trends in the industry, the sessions offered valuable insights and opportunities for knowledge exchange! Our interactive exhibition provided a platform for networking and collaboration among industry professionals, allowing attendees to explore the latest products and services.

About SMTA

SMTA is an international association for electronics engineering and manufacturing professionals. SMTA offers exclusive access to local, regional, domestic and global communities of experts, as well as accumulated research and training materials from thousands of companies dedicated to advancing the electronics industry. SMTA currently is comprised of 55 regional chapters around the world and 29 local vendor exhibitions (worldwide), 10 technical conferences (worldwide), and one large annual meeting.

Some of the greatest benefits come from the SMTA’s mission of the sharing of knowledge and best processes by bringing educational content and a global network to local regions. It’s a wonderful opportunity for young students and young professionals to connect to their field domain and potential recruiters.

Formatting Advanced Packaging for the AI Era

The development of Advanced Package Technology is undergoing a massive change because Electrical System Architects are directly driving package performance requirements, something which has never happened before. Previously System Architects designed circuits around package limitations because pushing package technologies outside of their “comfort zones” often led to undesirable results.  With the rise in transistor costs and the need to improve power efficiency, Silicon Architects have little choice but to push advanced package technologies well beyond their comfort zones.

The Wafer-Level Packaging Symposium will bring together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies. Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the Wafer-Level Packaging Symposium will be at the forefront of packaging technology evolution. The conference will feature attendees from around the globe in the heart of Silicon Valley to immerse themselves in the latest technology and business trends.

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