CISCO ASIC Success with Synopsys SLM IPs

Cisco’s relentless push toward higher-performance networking silicon has placed extraordinary demands on its ASIC design methodology. As transistor densities continue to rise across advanced SoCs, traditional design-time guardbands are no longer sufficient to ensure long-term reliability, consistent performance, and efficient power consumption. Instead, these chips require deep, real-time observability throughout the operational lifecycle. The challenge is addressed through Cisco’s adoption of Synopsys Silicon Lifecycle Management (SLM) IPs. The company’s latest Silicon One ASICs integrate a broad set of embedded monitors and analytics capabilities that collectively redefine what in-silicon visibility looks like.

Modern networking ASICs operate under highly dynamic conditions. Voltage and temperature fluctuate constantly inside dense logic blocks, and variations in process corners across a single die can influence timing behavior in subtle but meaningful ways. Cisco faces additional pressure because its chips target mission-critical infrastructure where uptime, predictability, and performance efficiency are paramount. According to the success story, transistor aging, exacerbated by thermal and voltage cycling, can reduce timing slack over time, making continuous monitoring essential to safeguard performance margins.

To address these challenges, Cisco deployed a comprehensive suite of Synopsys SLM IPs across its newest ASIC platforms. At the center of this strategy is the Process, Voltage, and Temperature Monitor (PVT) subsystem, orchestrated by the PVT Controller (PVTC). The PVTC aggregates data from multiple distributed sensors, enabling a unified view of environmental and process states across the chip. With this real-time data, the system can support dynamic voltage and frequency scaling, optimizing power and performance based on immediate conditions rather than worst-case assumptions.

Several sensor types feed into this controller. The Process Detector identifies variations across silicon regions, helping Cisco tune performance and understand die-to-die differences. Voltage Monitors track fluctuations in supply rails, ensuring critical blocks operate within safe thresholds. Distributed Temperature Sensors and thermal diodes provide granular thermal maps, improving both thermal management and temperature-dependent calibration. Collectively, these sensors give unprecedented visibility into what is happening inside every major functional quadrant of the ASIC.

Beyond PVT data, Cisco uses the Path Margin Monitor to watch critical timing paths in real time. Instead of relying solely on static timing analysis or margin-heavy design, PMM enables early detection of timing degradation due to aging or unexpected workload conditions. Meanwhile, the Clock Delay Monitor focuses on SRAM behavior, measuring access times and ensuring that memory blocks meet their intended timing specifications during actual operation.

The results are substantial. Cisco has achieved significantly enhanced real-time observability across its ASIC designs, enabling dynamic optimization of power and performance rather than fixed guard-banding. The continuous monitoring of path margins and aging allows proactive reliability management, helping extend the usable lifespan of the silicon. The insights generated not only improve today’s chips but also feed back into future design cycles, refining models and guiding architectural decisions. The modular nature of Synopsys SLM IPs also ensures Cisco can tailor sensor density and placement to each ASIC’s unique requirements, balancing efficiency with coverage.

Bottom line: Cisco plans to leverage Synopsys Silicon.da analytics to mine the vast data produced under diverse operating conditions. This data-driven feedback loop positions Cisco to continue advancing high-performance networking silicon while reducing risk and improving consistency across its product lines. Through its collaboration with Synopsys, Cisco has established a new benchmark for ASIC observability, reliability, and lifecycle optimization in the networking domain.

https://www.synopsys.com/success-stories/cisco-enhances-asic-slm.html

Also Read:

How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s

WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity

Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution