Synopsys @ #51DAC Must See!

Accelerating Innovation—that has been at the heart of Synopsys’ commitment to its customers for more than 25 years. As a leader in EDA and semiconductor IP, Synopsys’ software, IP and services help engineers address their design, verification, system and manufacturing challenges and accelerate their innovations. Since 1986, engineers around the world have used Synopsys technology to design and create billions of chips and systems. What will you design next? Visit Synopsys at Booth #1133 to learn more about the newest solutions available to help you to accelerate your innovations.

Special Events
Register early for these Synopsys events at DAC. View an event below for more information and to reserve your place:
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| valign=”top” | June 2
| valign=”top” | Samsung/Synopsys Breakfast
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| valign=”top” | June 2
| valign=”top” | IC Compiler/IC Compiler II Lunch: Addressing Advanced Design Needs
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| valign=”top” | June 2
| valign=”top” | Circuit Simulation Lunch: Complex Mixed-signal SoCs—How to Conquer the Next Verification Frontier
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| valign=”top” | June 2
| valign=”top” | International Microelectronics Olympiad Competition
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| valign=”top” | June 2
| valign=”top” | PrimeTime SIG Dinner: Accelerating Timing Closure with Advanced Technologies
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| valign=”top” | June 3
| valign=”top” | GLOBALFOUNDRIES Breakfast: Building an Open Ecosystem to Fuel IoT and Mobile Growth
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| valign=”top” | June 3
| valign=”top” | Verification Lunch: SoC Leaders Verify with Synopsys
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| valign=”top” | June 3
| valign=”top” | Custom Design Lunch: Innovations in Custom Design
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Synopsys provides innovative technology and solutions for implementation and verification. Visit us at Booth #1133 to find out more!

Demo Descriptions

Pre-registration is not required, but seating is limited and will be provided on a first-come/first-served basis. We recommend that you arrive 5-10 minutes prior to the demo session you are interested in attending.

Monday, June 2
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| align=”center” style=”width: 120px” | Time
| align=”center” style=”width: 250px” | Suite A
| align=”center” style=”width: 250px” | Suite B
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| 10:00 – 11:00
| IC Compiler/IC Compiler II
| Static/Formal Verification
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| 11:00 – 12:00
| PrimeTime
| Verification Compiler
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| 1:00 – 2:00
| DesignWare IP
| Coverity
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| 2:00 – 3:00
| PrimeTime
| ZeBu
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| 3:00 – 4:00
| Design Compiler
| Verification Compiler
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| 4:00 – 5:00
| Custom Design
| Coverity
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| 5:00 – 6:00
| IC Compiler/IC Compiler II
| Static/Formal Verification
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Demo Descriptions
Tuesday, June 3
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| [TABLE] cellpadding=”3″ cellspacing=”1″
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| align=”center” style=”width: 120px” | Time
| align=”center” style=”width: 250px” | Suite A
| align=”center” style=”width: 250px” | Suite B
|-
| 10:00 – 11:00
| Custom Design
| ZeBu
|-
| 11:00 – 12:00
| PrimeTime
| Coverity
|-
| 1:00 – 2:00
| Design Compiler
| Coverity
|-
| 2:00 – 3:00
| IC Compiler/IC Compiler II
| Verification Compiler
|-
| 3:00 – 4:00
| DesignWare IP
| Static/Formal Verification
|-
| 4:00 – 5:00
| Custom Design
| ZeBu
|-
| 5:00 – 6:00
| IC Compiler/IC Compiler II
| Verification Compiler
|-

|-

Demo Descriptions
Wednesday, June 4
[TABLE] style=”width: 620px”
|-
| [TABLE] cellpadding=”3″ cellspacing=”1″
|-
| align=”center” style=”width: 120px” | Time
| align=”center” style=”width: 250px” | Suite A
| align=”center” style=”width: 250px” | Suite B
|-
| 10:00 – 11:00
| Custom Design
| Verification Compiler
|-
| 11:00 – 12:00
| IC Compiler/IC Compiler II
| Static/Formal Verification
|-
| 1:00 – 2:00
| DesignWare IP
| ZeBu
|-
| 2:00 – 3:00
| Custom Design
| Verification Compiler
|-
| 3:00 – 4:00
| IC Compiler/IC Compiler II
| Static/Formal Verification
|-
| 4:00 – 5 :00
| Design Compiler
| ZeBu
|-

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Speakers Monday | Tuesday | Wednesday | Thursday
MONDAY, JUNE 2
IP PANEL 2.2:
What Large IP Companies Want
Track: IP
Time:10:30 a.m. to 12:00 p.m.
Location:Room 105

In recent years we have seen a considerable amount of acquisition activity by the large, public players in the semiconductor IP industry. At the same time we have seen an explosion in the formation of new, private IP companies. Listen to our moderator attempt to determine via public interview, the investment and acquisition strategies of three of the largest IP companies in the industry.
Moderator:

• Lucio Lanza, Lanza TechVentures, Palo Alto, CA

Panelists:

• Navraj Nandra, Synopsys, Inc., Mountain View, CA
• Martin Lund, Cadence Design Systems, Inc., San Jose, CA
• Farzad Zarrinfar, Mentor Graphics Corporation, Fremont, CA

Technology Exhibits Visit us at Booth #1133 to see these exciting technology exhibits.
HAPS[SUP]®[/SUP] Family of FPGA-Based Prototyping Solutions
The HAPS (High-performance ASIC Prototyping Systems) family of FPGA-based prototyping solutions provides an integrated and scalable hardware-software solution leveraged by design and verification teams to improve their ASIC design schedules and avoid costly device re-spins. Synopsys’ HAPS-70 system consists of a suite of modular, easy-to-use products for ASIC and SoC prototyping that include HAPS hardware components supported by an integrated software tool flow for design planning, implementation, partitioning and debug.
For more information, visit the Synopsys web site.
ZeBu Server-3
Learn how ZeBu Server-3, Synopsys’ new high-performance emulation system, helps SoC development teams speed hardware/software bring-up and full-chip verification with its industry-leading multi-megahertz performance. ZeBu Server-3 can improve productivity throughout the SoC development cycle with advanced use modes such as hybrid emulation with virtual prototypes for architecture validation and early software development, and transaction-based verification for high-performance, full-chip verification using complex virtual test environments and high-bandwidth transactors. ZeBu Server-3 offers a lower total cost of ownership, with low power consumption and small footprint resulting in 80-95% lower operating costs compared with other commercial emulators.
For more information, visit the Synopsys web site.

Design Tools for Application-Specific Processors (ASIPs)
This demo will show how Synopsys’ tools for the design of application-specific processors (ASIPs) enable more flexibility in SoC architectures. ASIPs serve as accelerators in processor-based SoCs, offering performance and energy characteristics similar to hardwired data-paths. Yet they offer software programmability, thus permitting late changes in the specification of the functions to be accelerated. This flexibility provides a key advantage for SoCs that have specialized processing requirements.
For more information, visit the Synopsys web site.

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