WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 694
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 694
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
)
            
800x100 Efficient and Robust Memory Verification
WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 694
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 694
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
)

Special Interest Group for HSPICE at DesignCon in Two Weeks

Special Interest Group for HSPICE at DesignCon in Two Weeks
by Daniel Payne on 01-13-2014 at 8:00 pm

DesignCon brings together engineers from around the world that are interested in IC design, package design and board design, plus the signal integrity issues of creating high-speed systems. In just two weeks there’s a Special Interest Group(SIG) just for users of HSPICE in their tool flow, and it meets for three hours during dinner in the evening from 6PM to 9PM on Tuesday, January 28th. I’ve blogged about this event in past years:

The SPICE world moves quickly, so Synopsys is busy adding new features and improvements each year, plus at this SIG you get to hear from real users of HSPICE, not the marketing droids. There are 13 EDA partners that create tools that use HSPICE for analysis, and you can stop by and chat with their AEs to find out how the integrations work.

[TABLE] cellpadding=”6″ cellspacing=”6″ style=”width: 600px”
|-
| align=”center” valign=”middle” |
Ansys

| align=”center” valign=”middle” |
Concept Engineering

| align=”center” valign=”middle” |
CST—Computer Simulation Technology

|-
| align=”center” valign=”middle” |
Helic S.A.

| align=”center” valign=”middle” |
Infiniscale

| align=”center” valign=”middle” |
IO Methodology, Inc.

|-
| align=”center” valign=”middle” |
Lorentz Solution

| align=”center” valign=”middle” |
MunEDA GmbH

| align=”center” valign=”middle” |
Orora Design Technologies, Inc.

|-
| align=”center” valign=”middle” |
Signal Integrity Software, Inc.
(SiSoft)

| align=”center” valign=”middle” |
Solido Design Automation Inc.

| align=”center” valign=”middle” |
Sonnet

|-
| align=”center” valign=”middle” |
Zuken

| rowspan=”2″ |
|-

Topics

You can expect to see at least four presentations covering topics like:

  • Signal integrity analysis
  • Power integrity analysis
  • Designing multi-gigabit serial links
  • New HSPICE features and improvements

You can even approach an HSPICE developer or manager and nag them about adding your favorite new feature. There’s nothing like a direct request to get engineering thinking about what’s important to add in the next release.

Registration

You need to register for this event online here. If you cannot make it to DesignCon this year, then stay tuned because I’ll have a link to a video recording of the HPSICE SIG and blog about it. Stay until the very end of the presentations and get a chance to win a prize, typically something cool like a tablet.

lang: en_US

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.