Lunch on Tuesday at DAC was sponsored by the IPL Alliance and thankfully this year they skipped the attempt at humor and focused on interoperable PDKs. Presenting companies include: Synopsys, Dongbu HiTek, TowerJazz, X-FAB and Si2. Having both OpenPDK and iPDK on the same platform does sound like a peaceful co-existence to me, although I wasn’t too sure about that one year ago.
In a nutshell the foundries don’t want to support multiple Process Development Kits (PDKs) because it uses up too much engineering time, instead they would prefer to create one PDK called an iPDK. The elephant in the room is that Cadence has a P-cell based PDK created with Skill code that kind of competes with what iPDK offers. So foundries acquiesce and create two PDKs, one for Cadence and another one for all of the other EDA vendors using iPDK technology.
FAQ
What is IPL 2.0?
IPL 2.0 is an updated release of IPL 1.0, the semiconductor industry’s first open standard for interoperable Process Design Kits (iPDKs). The IPL2.0 reference kit includes an iPDK developer’s guide, a sample 40-nanometer (nm) reference iPDK, a reference design and a user guide. IPL 2.0 uses the same specification of the standard and adds a new 40-nm reference iPDK in addition to the 90-nm reference iPDK in IPL 1.0. It is ready now for validation by IPL
Alliance members.
IPL 2.0 40nm reference iPDK download package – available for IPL Alliance members
IPL 1.0 90nm reference iPDK download package – available for public download at www.IPLnow.com
IPL 1.0 standard documents – available for IPL Alliance members
iCDF standard
Tcl callback standard
What is IPL Constraints 1.1?
IPL Constraint 1.1 is the open standard for interoperable design constraints. This is the result through the collaboration of IPL Constraint Working Group member companies including Altera, Ciranova, Mentor, Pulsic, SpringSoft, Synopsys and TSMC. Additionally, Xilinx and ST Microelectronics are acting in an advisory role. IPL Constraint 1.1 defines an open standard of the specifications for a set of design constraints and it is now available for validation by IPL Alliance members.
What is the IPL Alliance?
The IPL (Interoperable PDK Libraries) Alliance is an industry standard organization founded in April 2007 to establish an interoperable eco-system in custom design. The current focus is on interoperable PDK’s (iPDK) and interoperable analog constraints. IPL Alliance members collaborate to create and promote PDK standards to enable a single PDK to support multiple OpenAccess tools. For more information about the IPL Alliance and to join, please visit www.IPLnow.com.
Jingwen Yuan – Synopsys, Introduction
IPL is a non-profit organization with corporate sponsors, this is their 5th anniversary. IPL board members and early iPDK pioneers were recognized.
Charter: Create and promote standards for interoperable eco-system in custom design. iPDK and analog constraints are the focus.
Goal: A single PDK to support all OA tools. Reduce PDK development costs.
Progress: IPL 2.0 spec available in June 2012. IPL Constraints 1.1 available in Dec 2011.
A 40nm iPDK Reference Kit is available.
IPL 2.0 is available for members only now, public consumption by end of 2012.
IPL 1.1 constraints are for members only now.
Steps: Collaborate with SI2 Open PDK Coalition. Validate IPL 2.0 with alliance members. Enhanced IPL 1.1 constraints for general release.
Info – www.iplnow.com, LinkedIn group (over 500 members now). IPL Alliance booth at DAC this year, #1730.
Demand that your EDA and Foundry support iPDK.
Won-Young Jung (Dongbu HiTek, VP, Ph. D.)
Attracted to iPDK because of interoperability benefits (Laker, Custom Designer, Virtuoso).
New PDKs are developed with SKILL then migrated to iPDK. Supporting Cadence, Synopsys and SpringSoft through iPDK.
The iPDK development process starts with front-end to use scripts to create PyCells from Pcells. Start with Skill PDK then do iPDK (seemed like twice the work to me). Just at the start of creating iPDK.
WOrking on BCD 0.35um and 180nm in 2012. ESD devices are created as PyCells.
Ofer tamir (TowerJazz, CAD Director)
A global provider of specialty processes, Israel, CA and Japan. In the past 6 years the growth is 499%. RF, analog, CMOS image sensor, power management, MEMS, MCM.
Processes – 0.5um to 130nm.
iPDK ships with add-ons to allow designers to be successful.
iPDK development and QA flow, both SKILL and iPDK developed simultaneously with automated verification between the two kits. Layout is both Skill and PyCell based. Automated comparisons of layout for verification.
180nm process is available as an iPDK now, with two flavors: Standard, Image Sensor flow.
We created an Analog Reference Flow, version 1.0. Also, a Mixed Mode Reference design, version 2.0.
FOr the 180nm process node you start with a base platform, then can add Image Sensor or Digital. Example shown of the same IC design in Cadence and Synopsys layout tools.
A Pcell library has schematics, symbols, tech file, parameters and callbacks, CDF netlisting is non-standard (required multiple tries to get a correct netlist), PyCell layout, OA. MIssing standard on how to netlist in a unified way. A spec has been written on netlisting output by TowerJazz, should we have a sub-group within IPL?
Thomas Ramsch (X-FAB, Director of Design Support)
Pure play foundry for fabless, IDM and OEM with a focus on AMS using 1um to 130nm nodes. Three different fab locations. Markets include: Automotive, Opto, MEMS, Analog and High Voltage.
Modular process modules: HV, NVM, Analog, Digital.
PDK Support: Cadence, Mentor, Synopsys, Tanner EDA.
PDK includes many things: Technology libraries, primitive device libraries, simulation models, DRC/LVS decks, standard cell libraries, analog macro cell libraries, AMS environment, memory generators, NVM generators.
Create a Cadence Skill-based Pcells.
FOr Mentor a translator using an OA PDK translator.
Synopsys and Tanner EDA use Python based PyCells.
Synopsys PDK ready now, Tanner EDA PDK ready soon in 2012.
PDK development process requires verification of callbacks and Pcells.
Skill and Python layout cells are compared and verified, layout vs layout. Verification takes about 1,000 hours.
Benefits include about 4-10 times faster for defining an providing iPDKs.
Processes are automotive qualified and X-FAB is a member of IPL Alliance.
Ed Petrus (Si2 Vice Chair, and Mentor Graphics, Architect)
Former co-founder of CiraNova.
How should Si2 with OpenPDK (founded 2010) and IPL Alliance work together?
OpenPDK – to be created once and then translated into specific EDA vendor tools and specific foundry formats.
– Chair is Jim Culp from IBM. Technical Steering Group headed by Gilles Namur from ST.
– Working Groups: SYmbols, parameters, callbacks.
IPL Synergy – can we go from OpenPDK to IPL without translation of data?
Q&A:
Nick English (Si2) – We have a simulation integration working group, one contribution coming in and more invited. Want to avoid any duplication of work.
Srithar (Silicon Labs) – SKill to Python conversion, how elaborate is that effort?
A: It took X-FAB about one year to automate that step.
A: Skill Pcell to PyCell conversion is mostly automatic, but not very easy. Checking is automated.
Q: MangaChip – Not started developing iPDK yet because it takes too much time or cost. Why did you support iPDK?
A: (TowerJazz) – separate development of PyCells and Skill, then QA between the two PDKs. Double develop callbacks and cell layouts.
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