Rise Design Automation Webinar: SystemVerilog at the Core: Scalable Verification and Debug in HLS

Key Takeaways

• High-Level Synthesis (HLS) delivers not only design productivity and quality but also dramatic gains in verification speed and debug – and it delivers them today.
  • Rise Design Automation uniquely enables SystemVerilog-based HLS and SystemVerilog verification, reusing proven verification infrastructure.
  • The webinar features expert insights from verification methodology architect Mark Glasser, and Mike Fingeroff, HLS expert, presenting the technical content and a live demonstration.
  • Attendees will learn how to unify design, verification, and debug across abstraction levels without duplicating effort.

Register Here

High-Level Synthesis (HLS) and raising design abstraction have been proven to deliver significant productivity and value to design teams — faster design entry, improved architectural exploration, and tighter system-level integration. These benefits are real, but experienced users and teams often cite a different advantage as the most valuable: verification.

By enabling earlier testing, running regressions 30×–1000× faster than RTL, and simplifying debug, HLS can dramatically accelerate verification. The challenge, however, is that existing HLS flows rely on C++ or SystemC, often leaving verification disconnected from established SystemVerilog/UVM environments. This gap forces teams to bridge methodologies on their own and uncover problems only after RTL is generated — slowing adoption and raising risk.

Rise Design Automation addresses this directly by making SystemVerilog a first-class citizen in HLS. In collaboration with SemiWiki, Rise will host a webinar that demonstrates how teams can apply familiar SystemVerilog and UVM methodologies consistently from high-level models through RTL, simplify debug, and unify design and verification across abstraction levels. The live event takes place on Wednesday, October 8, 2025, from 9–10 AM Pacific Time.

The Webinar Presenters:

The session begins with Mark Glasser, a distinguished verification architect and methodology expert. Mark co-invented both OVM and UVM and is the author of the recently published book, Next Level Testbenches: Design Patterns in SystemVerilog and UVM (2024). He will provide historical and forward-looking context on how verification methodology has evolved and the need driving raising abstraction.

The majority of the session will be presented by Mike Fingeroff, Chief of HLS at Rise DA. With over 25 years of experience and as the author of The High-Level Synthesis Blue Book, Mike specializes in HLS, SystemVerilog, SystemC, and performance modeling. He will deliver the technical deep dive and a live demonstration of Rise’s flow.

Key Topics

The webinar will address how Rise enables:

• SystemVerilog for HLS – untimed and loosely timed modeling and the constructs synthesized into RTL.
  • Verification continuity – applying SystemVerilog methodologies consistently from high-level models through RTL.
  • Mixed-language and mixed-abstraction simulation – explain the automatically generated adapters that bridge between HL and RTL and how to mix-and-match in verification including UVM.
  • Advanced debug features – HL↔RTL correlation, transaction-level waveforms, RTL signal visibility, and synthesized assertions and coverage.
  • Familiar debug practices – including $display support and line-number annotations for RTL signals.

A highlight of the session will be a live demonstration, where attendees will see a design example progress from high-level verification through RTL, showcasing methodology reuse and debug continuity.

To Learn More

If you’re looking to accelerate verification, reduce duplicated effort, and understand how to apply your existing SystemVerilog/UVM expertise in an HLS context, this webinar will step you through the code.

Learn More and Register Here

Don’t miss the opportunity to see how SystemVerilog at the core of HLS can streamline your design process and verification flow.