When I first started doing circuit design with Intel at the transistor level back in the late 1970’s we had exactly two EDA tools at our disposal: an internally developed SPICE circuit simulator, and a commercial IC layout system. Over the years at Intel the internal CAD group added many more automation tools: gate level simulator, cycle based simulator, DRC, LVS, PLA generator, schematic capture, IC layout. The point is that many IC and SoC companies have internal CAD groups that are tasked with creating tools to make the design and management of IP easier for the design groups. From a management perspective someone has to be asking the question, “Should we develop this automation ourselves, or just use something off the shelf that is commercially supported?”
Focusing on the area of IC design management (DM) our semiconductor industry has often coded their own version control systems that made a lot of sense at the time the need was identified. A common architecture to start with for data management uses a single server per project as shown below:
There are some limitations when using a server per project for design management, like:
- Difficult to share or re-use semiconductor IP across projects
- Little scaling
- Limited performance
A more modern approach to DM tools is to re-use existing version control software, have a centralized architecture, and scale across an entire organization. Here’s a picture of this architecture:
Some of the immediate benefits of this centralized approach is how easy it is to share IP and updates across the entire company.
OK, so the modern approach looks better than the server per project idea, so which commercial DM tool should I even consider? Well, first consider selecting a vendor that gives you a choice in file versioning system instead of locking you into a proprietary file versioning system. The idea is that you can choose a commercial file versioning system that has the best scalability and reliability to handle your biggest SoC designs easily. Proprietary version control systems don’t scale well to support the giga-size volumes that modern SoCs demand.
Being able to easily share all of the semiconductor IP within your company to all projects is a big plus with the centralized server architecture, because there are no more silos of data to stitch together. With a Platform Based Design methodology each of your project teams can get quick access to the most updated version of IP and support files, then get alerts when there’s been any updates. With a Single Source of Truth your company is going to spend less time on IT and support costs.
Here’s a summary of what you should be looking for in a modern, IP management system:
That’s quite the list of IP management requirements and one EDA vendor that meets this list is Methodics. Engineers at Methodics have created ProjectIC that enables IP centric Platform Based Design using the concept of Single Source of Truth by handling all of your IC project:
- Design Files
- IP Versions
- Bug Tracking
- Labels and Custom Fields
- Release Management
- IP Usage Tracking
- Workspace Tracking
The technology to enable file sharing while reducing the size and network bandwidth by up to 90% is called Warpstor, and it’s going to come in handy when your SoC workspace exceed 100GB. Best of all Warpstor is invisible to design engineers.
One of the best file versioning systems around is Perforce Helix because it has server technology that supports tens of thousands of users.
Cadence IC design users will be right at home with Methodics because the VersIC design tool integrates ProjectIC and Perforce into their familiar user interface.
Now that you know a bit more about DM from Methodics with their Single Source of Truth, you get to compare that versus any internal or proprietary system in use now. Many design groups opt for a commercial tool because of the features, performance, reliability and integration. Read the full White Paperon this topic.
Related blog – Requirements Management and IP Management Working Together
Related blog – 5 Reasons Why Platform Based Design Can Help Your Next SoC