My Conversation with Infinisim – Why Good Enough Isn’t Enough

My recent post on a high-profile chip performance issue got me thinking. The root cause of the problem discussed there had to do with a clock tree circuit that was particularly vulnerable to reliability aging under elevated voltage and temperature. Chip aging effects have always got my attention. I’ve lived through a few of them in my career and they are, in a word, exciting. Perhaps frightening.

This kind of failure represents a ticking time bomb in the design. There are many such potential problems embedded in lots of chip designs. Most don’t ignite, but when one does, things can get heated quickly. I made a comment at the end of the last post about Infinisim and how the company’s technology may have avoided the issue being addressed. I decided to dig into that topic a bit further to better understand the dynamics at play with clock performance. So, I reached out to the company’s co-founder and CTO. What I got was a master class in good design practices and good company strategy. I want to share my conversation with Infinisim and why good enough isn’t enough.

Who Is Infinisim?

You can learn more about Infinisim on SemiWiki here. The company provides a range of solutions that focus on accurate, robust full-chip clock analysis.

Several tools are available to achieve this result. One is SoC Clock Analysis that helps to accurately verify timing, detect failures, and optimize performance of the clock in advanced designs. Another is Clock Jitter Analysis that helps to accurately compute power supply induced jitter of clock domains – a hard-to-trace problem that can cause lots of problems. And finally Clock Aging Analysis that helps to accurately determine the operational lifetime of power-sensitive clocks. It is this last tool that I believe could have helped with the chip issue discussed in my prior blog.

The tools offered by Infinisim use highly accurate and very efficient analysis techniques. The approach goes much deeper than traditional static timing analysis.

My Conversation With the CTO

I was able to spend some time speaking with Dr. Zakir H. Syed, co-founder and chief technology officer at Infinisim. Zakir has almost 30 years of experience in EDA. He was at Simplex Solutions (acquired by Cadence) at its inception in 1995 through the end of 2000.  He has published numerous papers on verification and simulation and has presented at many industry conferences.  Zakir holds an MS in Mechanical Engineering and a PhD in Electrical Engineering, both from Duke University.

Here are the questions I posed to Zakir and his responses.

It seems like Infinisim’s capabilities can provide the margin of victory for many designs. How are you received when you brief potential customers?

 Their response really depends on past experiences. If they’ve previously encountered issues—like anomalous clock performance, timing challenges, or yield problems—they tend to quickly see the value Infinisim brings and are eager to learn more. In my experience, these folks are few and far between, however.

This is a bit surprising. Why do you think this is the case?

It’s an interesting point. The issue isn’t that better performance isn’t desirable; it’s that there’s a general trend to accept less-than-optimal performance as the norm. Over time, parameters like timing, aging, jitter, yield, and voltage have been treated as “known quantities” and design teams rely on established margins to work within these expectations.

I’m beginning to see the challenge. If design teams are meeting the generally accepted parameters, why rock the boat?

Exactly. If the design conforms to the required margins, all is well. Designers are rewarded for meeting schedules. CAD teams are recognized for delivering an effective flow. And this continues until there is some kind of catastrophic failure. When that “ticking time bomb” goes off, suddenly every assumption is questioned, and a deep analysis begins.

I get your point. I wrote a blog recently that looked at a high-profile issue that was traced back to clock aging.

Yes, that issue could likely have been discovered with our tools, before the chip was shipped to customers. In that case, aging effects came into play under certain operating conditions. Since N-channel and P-channel devices age differently, the result was a clock duty cycle that began to drift from the expected 50/50 duration. Once the asymmetry became large enough, circuit performance began to fail.

So, what you don’t know can hurt you.

You’re right. But there’s also a bigger opportunity here. It’s not just about preventing catastrophic failures. Advanced nodes are costly, and we pay for that performance. By thoroughly examining circuit behavior across all process corners, we can leverage that investment to its fullest potential instead of leaving performance on the table with excessive margins. The same goes for yield, which directly impacts profitability. In today’s competitive chip design landscape, accepting less performance often means losing out on market share.

OK, the light bulb is going off. Now I see the bigger picture. Using tools like Infinisim’s doesn’t just prevent failures; it’s a strategic move toward maximizing profitability and competitiveness.

I think you’ve got it. When more people within a company—from engineers to executives—embrace this mindset, it leads to a stronger, more competitive organization. By challenging the status quo, companies can achieve more and realize their full potential.

To Learn More

You can learn more about the integrated flow offered by Infinisim here.  My conversation with Infinisim made it clear why good enough isn’t enough.