CTO Interview: Dr. Zakir Hussain Syed of Infinisim

Zakir Hussain is a co-founder of Infinisim and brings over 25 years of experience in the Electronic Design Automation industry. He was at Simplex Solutions, Inc. (acquired by Cadence) at its inception in 1995 through the end of 2000.  He has published numerous papers on verification and simulation and has presented at many industry conferences.  Zakir obtained his Masters degree in Mechanical Engineering and a PhD in Electrical Engineering from Duke University.

What is the Infinisim backstory?
Infinisim, Inc is a privately funded EDA company founded by industry luminaries with over 50 years of combined expertise in the area of design and verification. Infinisim customers are leading edge semiconductor companies and foundries that are designing high-performance SoC, AI, CPU and GPU chips.

Infinisim has helped customers achieve unprecedented levels of confidence in design robustness prior to tape-out. Customers have been able to eliminate silicon re-spins, reduce chip design schedules, and dramatically improve product quality and production yield.

What market segments are you targeting?
The simple answer is leading edge complex SoCs, multi giga hertz CPU, GPU, and domain specific chips (bespoke silicon) with high core counts but we look at three distinct capabilities that our tools provide:

SoC Clock Analysis
Our leading edge clock analysis solution helps customers accurately verify timing, detect failures, and optimize performance of the clock.

Clock Jitter Analysis
Our specialized jitter analytics solution helps customers accurately compute power supply induced jitter of clock domains.

Clock Aging Analysis
Our Clock Aging Analysis helps customers accurately determine the operational lifetime of power-sensitive clocks.

For SoC clock analysis, the leading edge mobile SoC market is a great example where power consumption is critical. For aging, Automotive and other mission critical markets (especially at 6nm and below) where the product lifespan is 5 or more years. For Jitter, high frequency and high performance chips like CPUs, GPUs and large bespoke silicon with lots of cores that require strict accuracy.

What keeps your customers up at night? 
Tape-out confidence keeps everyone up at night! The cost of tape-out is very high below 7nm so errors cannot slip by. For example: timing related rail to rail failures and duty cycle distortion (DCD). Also jitter and aging analysis.

Customers are always looking for a competitive advantage over what everyone else is doing. Tightening margins on performance, power, and area is a risky proposition without a sign-off proven clock analysis tool. Clocks are critical, some designs are all about the clocks and guard banding your way out of complexity hurts the competitive positioning of your product. Especially if your competitor is already working with Infinisim.

What makes your product unique?
The founding Infinisim team had many years experience with IR drop analysis doing very large power grids. Fast Spice did not work since you had to chose between accuracy and speed so a custom spice engine was developed. Rather than approach the general SPICE market, the Infinisim tool set and methodology was developed specifically for clock tree analysis. This is a critical difference between Infinisim and general purpose EDA tools.

Clock is a unique problem and requires a unique tool. Infinism has a special purpose simulator designed specifically for SoC clock analysis, clock jitter analysis, and clock aging analysis. Speed AND capacity AND full SPICE accuracy is the focus so there is no trade off like traditional simulators.

What’s next for the company?
Three things:

1) We are working closely with customers on increasing accuracy, speed, and capacity for the new FinFET nodes. Infinisim is a sign off tool at 14nm down to 5nm and 3nm is in process. The complexity of chips is increasing so this will be a never ending challenge for clocks.

2) We are working closely with customers and foundries on GAA processes which will require a new set of capabilities. FinFET models are public domain and very accessible. GAA models are proprietary and will be tied closely to foundries versus EDA tool companies.  GAA models are much more complicated with more equations due to changing conductance, capacitance, and more non linear effects at the device level.

3) We are collaborating with customers and cloud providers on a cloud based Infinisim solution.

How do customers engage with Infinisim?
Customers generally approach us with a clock problem. Since Infinisim is a single solution evaluations are fairly easy using a targeted approach on customer circuits. For more information or a customer engagement you can reach us at http://infinisim.com/.

Also Read:

Clock Aging Issues at Sub-10nm Nodes

Analyzing Clocks at 7nm and Smaller Nodes

Methodology to Minimize the Impact of Duty Cycle Distortion in Clock Distribution Networks