Power-Aware Verification in Mixed-Signal Simulation

My Samsung Galaxy Note 2 phone lasts about 1.5 days on a single battery charge, thanks in part to the clever power conservation approaches like when the screen is automatically dimmed then turned off after no activity. Mobile phones and many other battery-powered devices used today all need power-saving designs, which then means that engineers needs to verify the power management approaches. The Unified Power Format (UPF) standardized as IEEE 1801-2009 or 1801-2013 is a popular way to annotate your design with both the power and power control intentions.

What if you wanted to take into account the analog effects of the power management blocks? UPF doesn’t cover that, so you’re still open to errors in the design and verification of your power distribution network and verification of power states. Engineers at Infineon and Mentor Graphics have created a methodology to extend UPF to include mixed-signal verification, presenting a paper at DVCon Europeon October 14, 2014 and also in a recentWhite Paper.

Here’s the proposed power-aware mixed-signal verification environment:

With this type of verification environment the analog power supplies get synchronized with the power state of the UPF power domain, so it’s possible to reuse the standard UPF constructs. The mixed-signal verification tool elaborates the analog-UPF boundary, and then inserts the Power-Electrical (P2E) and Electrical-Power (E2P) connect elements.

Tire Pressure Monitoring System

Infineon engineers used the power-aware, mixed-signal verification on a tire pressure monitoring system (TPMS), shown in the following block diagram:

This product has ten power domains, multiple operating modes, and multiple power states like:

• Low-frequency
• Low-power
• Ultra-low power
• High performance (micro Amps)
• Power down mode (a few hundred nan Amps)
• Standby mode

UPF helps define the power intent during physical implementation of the digital parts of the TPMS design. The on-chip voltage regulators create and regulate voltages ranging from 1V to 5V.

Related – Transceiver Verification of a 20nm Altera FPGA Device

Previous Approach

A manual modeling approach was used previously where the digital part of the design was wrapped in a model (blue areas), then digital signals interfaced to analog with power-conversion models (pentagon shapes).

Manually editing a netlist and inserting power conversion model instances takes time, is error prone, and may not even match the actual power distribution network used by UPF. With this approach you couldn’t check for proper level shifting, or isolation and retention cell placement.

New Approach

With the Mentor simulator Questa ADMS you can use a power-aware mixed-signal verification flow. The simulator inserts the boundary elements between UPF and analog ports, keeping the power state and value in sync between the analog and digital domains. During verification of DVFS (Dynamic Voltage and Frequency Scaling) states of the design, the A2D and D2A logic boundary element include the primary power and ground port state plus the value of power domain logic signal belongs to.

Here’s what the power-aware logical boundary elements look like:

With this approach we don’t need the power conversion models, because the power information comes straight from UPF instead. With an analog-on-top methodology there is still a wrapper used.

Related – Coverage Driving Verification for Analog? Yes, it’s Possible

For the highest verification accuracy a SPICE netlist was used for the custom power switches in order to see the voltage switching and control sequence timing.

An E2P boundary element helps define the power net state:

Simulation results show the transition from a High Performance state to Power Shutoff, and then to a Low Power state:

With this new approach we can verify that:

• Correct level shifter units are inserted
• Proper isolation behavior
• Proper retention behavior
• Assertions are working

Summary

It’s now possible to use a power-aware, mixed-signal verification methodology by extending a UPF flow. Benefits of this flow include faster verification times, higher accuracy of analog design units, verification of the actual power architecture, verification of the power states, and verification of power state transitions.

Read the complete White Paper here.

Related: Improving Verification by Combining Emulation with ABV

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