Generative AI Comes to High-Level Design

I’ve watched the EDA industry change the level of design abstraction starting from transistor-level to gate-level, then RTL, and finally using High Level Synthesis (HLS). Another emerging software trend is the use of generative AI to make coding RTL more automated. There’s a new EDA company called Rise Design Automation that enables design and verification beyond RTL, so I attended their recent webinar to learn more about what they have to offer.

Ellie Burns started out with an overview of the semiconductor market and how trends like AI/ML, 5G, IoT and hardware accelerators are driving then landscape. RTL design techniques and IP reuse have done OK, but there is an insatiable demand for new designs and larger designs amidst a general engineering shortage.

What Rise offers is a new, three-prong approach to meet the market challenges:

Their generative AI is an assistant that automatically creates SystemVerilog, C++ or SystemC code based on your prompts. An agent also runs high-level synthesis and verification, saving time and effort. There’s even an agent for iterative performance tuning and optimization tasks.

This high-level code is synthesized into RTL, and using high-level verification can be up to 1,000X faster than RTL verification. Using this flow enables debug, analysis and exploration more quicky and thoroughly than an RTL approach. System architects get early, executable models to explore architectures. RTL designers can re-use system models, and reach PPA optimization faster. Verification engineers start verifying much earlier and benefit from auto-generated adaptors/transactors. Even the software engineers use the virtual platform for early access to accurate hardware behavior, and their model is always in sync with the hardware.

Mike Fingeroff, Chief of HLS at Rise was up next, showing how the high-level agents work with human-in-the-loo using existing pre-trained LLM’s plus a specialized knowledge base. The pre-trained LLM’s eliminate the need for any sensitive RTL training data. HLS converts SystemVerilog, C++ or SystemC into synthesizable RTL, inserts pipeline registers to meet timing, adds dataflow control, enables exploration and even infers memories.

Their HLS synthesis creates RTL, uses constraints for power, performance and area while optimizing with a technology aware library. Here’s the architecture that Rise has:

Alan Klinck, Co-founder of Rise DA, talked about agent-based generative AI for hardware design in three parts:

• Rise Advisor – prompts used for tasks and questions, expert assistance, accelerate code development
• Rise HLS Agent
• Rise Optimization Agent

For an example case he showed us hls4ml, a Python package for machine learning inference in FPGAs.

A live prompt typed was, “How do I make my HLS design synthesizable?”

The Rise system is modular, so you can even use your own language models. Their knowledge base plus language models reduces hallucinations, improving the quality of results. The language models can run on-premises or in the cloud, your choice, and there is no training going on with your tool usage. Using a consumer GPU like the NVIDIA 4090 is sufficiently powerful to run their tools. You go from HLS to RTL typically in seconds to minutes, so it’s very fast.

For the live demo they used the Visual Studio Code  tool on a loosely timed design with some predefined prompts, and as they asked questions and made prompts we saw newly generated code, ready for HLS. Trade-offs between multiple implementations was quickly generated for comparisons to find the optimal architecture.

Summary

I was impressed with an EDA vendor running their tool flow live during a webinar, instead of pre-canned screenshots. If you’ve considered improving your familiar RTL-based design flow with something newer and more powerful, then it’s likely time to look at what Rise DA has to offer. The engineering team has decades of experience in EDA and HLS, plus they’ve added generative AI to the flow that now benefits both design and verification engineers.

View the replay of their webinar online.

Related Blogs

• Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
• An Imaginative Approach to AI-based Design
• CEO Interview: Badru Agarwala of Rise Design Automation