Last year at DAC, we launched the RTL Signoff platform and our customers responded enthusiastically. We even had a few other EDA companies follow our lead. So what have we been up to since then?
Visit us at DAC this June and learn how we have expanded our industry leading RTL Signoff solutions to handle the next set of challenges in SoC design. Building on the success of our IP Signoff solution, we now offer a unique solution for SoC Signoff. This includes performance and capacity for billion+ gate designs through intelligent abstraction of models. A growing number of SoC design teams have standardized on our solutions and realized significant productivity gains.
Join us at the Atrenta booth #1933 to learn how you can benefit from the next generation of RTL Signoff solutions.
IP Signoff
Quality of incoming IP continues to be a major pain point for SoC designers. The challenges are not limited to just third-party IP, but also exist with internal IP blocks. Learn how the Atrenta IP Kit, built on the industry-standard SpyGlass® platform, solves this problem with a standardized set of design and verification checks along with an automated methodology. All of the results are summarized in easy-to-read HTML IP signoff reports.
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SoC Signoff
A billion+ gate SoC requires a sophisticated methodology for incoming IP inspection and integration; performance and capacity through abstraction; feasibility across various domains; and verification at the top level. Learn how the Atrenta solutions provide a holistic approach to RTL SoC Signoff, thus minimizing iterations at later stages of implementation.
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SpyGlass Platform
Late-stage surprises in the implementation cycle can delay tapeout and erode profitability. See the latest high performance and low noise advancements in the RTL Sign-off solution for billion+ gate SoCs. Achieve high confidence RTL Signoff with the SpyGlass platform by analyzing structural, functional, CDC, timing, power, DFT and physical issues.
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BugScope
Uncovering corner-case bugs, IP integration errors, and functional coverage holes prior to RTL signoff is critical to SoC verification success. With minimal effort, BugScope™ solution streamlines SoC integration, combining automatically generated assertion and functional coverage properties, with verification metric apps, helping engineers decide when verification is truly complete.
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SpyGlass Power
Energy savings requirements of mobile and networking products are putting extreme pressure on design teams. Taming the power consumption of your next chip requires a complete power management solution. See how accurate estimation, advanced optimization of RTL and verification of power intent from RTL to post-layout, can be achieved using the SpyGlass integrated power solution.
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SpyGlass Constraints
Design closure on today’s chips can require tens of thousands of constraints. Incomplete or inconsistent timing constraints impact timing closure, clock crossings, and power consumption. Incorrect timing exceptions can cause metastability, and ultimately, chip failure. Reduce your design risk and enable timing constraints, signoff at RTL with SDC validation, management, and verification of false / multi-cycle paths using unique formal techniques. Our patented constraints management technology addresses multi-mode and SoC integration.
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SpyGlass CDC & Advanced Lint
With up to 100 different clock domains in a typical SoC, integration is critically dependant on ensuing that the clocks are analyzed and validated across all of these domains. Learn how you can Signoff CDC verification of a billion gate design with easy setup and best-in-class signal to noise ratio. Achieve functional CDC verification closure using Hybrid CDC verification with formal techniques and functional simulation. Also learn how to formally analyze and verify initialization, finite state machines, synchronous FIFOs, and dead-code as well.
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SpyGlass DFT, DSM, MBIST
Testability is critical to the success of every SoC design. In this session, you will learn about Atrenta’s popular RTL testability solution for advanced technology nodes from 28 to 14nm, and how to improve stuck-at and at-speed coverage early in the process for both the block and SoC levels. Additionally, we will show you how you can easily insert memory BIST structures automatically at RTL.
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GenSys
Managing your RTL is no longer feasible with good old VI or Emacs. Learn how you can address the demanding requirements for RTL restructuring due to physical / power domain re-partitioning, FPGA prototyping, ECOs and architecture changes with an easy to use and automated flow using GenSys® solution. See how you can automate the assembly of your chip at the architectural level as well.
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SpyGlass Physical
The configuration of the RTL you send to implementation can have a major impact on the layout congestion and routability of your design. In this session you can learn how RTL verification against physical rules can identify structural design violations. Unique data flow analysis and physical topology constraints allow designs to easily assess floorplan quality across multiple configurations. See how designers are able to analyze, debug and optimize critical timing paths, macro placement, and routing congestion; handing off an initial floorplan to the back-end that will ensure predictable design closure.
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MONDAY June 02, 10:30am – 12:00pm | Room 101
1.2 A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality
Speaker: Anuj Kumar – Atrenta, Noida, India
Authors: Andy Wu – Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan
MONDAY June 02, 4:30pm – 6:00pm | Room 101 (Presentation)
5.3 CDC Aware Power Reduction for Soft IPs
Speaker: Amit Goldie – Atrenta, Noida, India
Authors: Ritesh Agrawal – Freescale Semiconductor, Inc., Noida, India
Amit Goldie – Atrenta, Noida, India
TUESDAY June 03, 12:00pm – 1:30pm | Room 100
301.4 SoC Connectivity Checks – Driving Design Intent Validation
Speaker: Subhra Bandyopadhyay – Cisco Systems, Inc., San Jose, CA
Authors: Subhra Bandyopadhyay – Cisco Systems, Inc., San Jose, CA
Jayanth S. Mekkoth – Cisco Systems, Inc., San Jose, CA
TUESDAY June 03, 4:00pm – 6:00pm | Room 105
38.5 The Evil’s in the Edits
Speaker: William Wallace – Texas Instruments, Inc., Dallas, TX
Authors: William Wallace – Texas Instruments, Inc., Dallas, TX
Nitin Jayaram – Texas Instruments, Inc., Dallas, TX
Nitin Mhaske – Atrenta Inc., San Jose, CA
WEDNESDAY June 04, 1:30pm – 3:00pm | Room 101
59.3 Effective RTL Coding Rules to Avoid Simulation Shoot-Thru
Speaker: Udit Kumar – STMicroelectronics, Greater Noida, India
Authors: Udit Kumar – STMicroelectronics, Greater Noida, India
Bhanu Prakash – STMicroelectronics, Greater Noida, India
Olivier Florent – STMicroelectronics, Grenoble, France
Paras Mal Jain – Atrenta Inc., Noida, India
Anshu Malani – Atrenta Inc., Noida, India
Shaker Sarwary – Atrenta Inc., San Jose, CA
IP Workshop:
SUNDAY June 01, 1:00pm – 5:00pm | Room 202
WORKSHOP: IP Workshop: Driving Quality to the Desktop of the DAC Engineer
Organizer: McKenzie Mortensen – IPextreme, Campbell, CA
Speakers: Robert Beanland – Atrenta Inc., San Jose, CA
Steve Chen – Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan
Michael Cizi – IPextreme, Munich, Germany
Neil Gregie – Sonics, Inc., Chicago, IL
Michael Johnson – Atrenta Inc., San Jose, CA
John Molyneux – Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA
Warren Savage – IPextreme, Campbell, CA
Randy Smith – Sonics, Inc., Milpitas, CA
Anuj Kumar – Atrenta, Noida, India
Co-sponsored Parties:
HOT IP Party
(6:30pm private reception)
Monday, June 2, 2014
7:30pm – 12:30am
Slim’s
San Francisco
Stars of IP Party
(Private, invitation-only event)
Tuesday, June 3, 2014
8:00PM – 1:00AM
Local Edition, Historic Hearst Building
San Francisco
About Atrenta
Atrenta’s SpyGlass Predictive Analyzer® significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred forty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScopeâ„¢, verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
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