Sigasi at the 2024 Design Automation Conference

Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.

The traditional HDL workflow cannot accommodate the massive amounts of design specifications from GenAI creations, high-level synthesis results, and other complex SoC IP. These new levels of abstraction need to plug and play alongside large HDL files—that contain functionality created with domain-specific knowledge—to integrate hundreds of billions of transistors on a chip.

The comprehensive Sigasi Visual HDL portfolio is an HDL platform able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress. They can easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. SVH does so by standardizing the concept of an HDL design project, bringing simulation and synthesis projects into a world of integrated development, synchronous visualization, and shift-left validation.

Integrated Development: SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE, according to Stack Overflow’s 2019 survey, with a rich marketplace of productivity tools. It includes sophisticated applications to easily use git and GitHub Source Control Management, as well as a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.

Synchronous Visualization: SVH lets users move seamlessly through hierarchy views and graphics that update instantaneously as they make changes in their code.

Shift-Left Validation: SVH flags problems while users enter HDL code. Starting with syntax and semantics, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses.

SVH comprises a tiered portfolio, offering three commercial editions meant to meet specific SoC design and verification challenges. The new offering also unveils Sigasi’s new AI chatbot, SAL, a chatbot that works with a local model or a remote OpenAI API and can generate, check, and explain HDL code. Each tier of SVH offers a comprehensive package of features, including type-time syntax and semantic checks and guardrails that enforce coding styles, policies, and standards. Regardless of which tier they use, engineers receive instant feedback and warnings for all files associated with a project.

Additionally, Sigasi offers a fully functional Community Edition that lets users explore its features for non-commercial uses, especially students and teachers learning and teaching the fundamentals of HDL design.

Sigasi will fly its new logo and tagline “Put Your Semicolons to Work” while exhibiting and demonstrating Sigasi Visual HDL at DAC Booth #2416 (second floor). DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

More details can be found on the Sigasi website or by emailing sales@sigasi.com.

To arrange a demo or private meeting to talk about Sigasi Visual HDL, send an e-mail to: dacmeeting@sigasi.com.

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