Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.
The traditional HDL workflow cannot accommodate the massive amounts of… Read More
Dieter Therssen obtained his master’s degree in Electronics Engineering from KU Leuven in 1987. He started his career as a hardware design engineer, using IMEC’s visionary tools and design methodologies in the early days of silicon integration.
Since then, Dieter developed his career across many digital technologies,… Read More
Semiconductor IP re-use is a huge part of the productivity gains in SoC designs, so instead of starting from a clean slate most chip engineers are re-using cells, blocks, modules and even sub-systems from previous designs in order to meet their schedule and stay competitive in the market place. But what happens when you intend to… Read More
When I was at Atrenta, we always thought it would be great to do as-you-type RTL linting. It’s the natural use model for anyone used to writing text in virtually any modern application (especially on the Web, thanks to Google spell and grammar-checks). You may argue that you create your RTL in Vi or EMACS and you don’t need no stinking… Read More
