Sigasi September Productivity Hacks Workshop

Sigasi September Productivity Hacks Workshop
by Admin on 08-15-2022 at 3:17 pm

Thursday, September 15, 2022, at 11am CEST/10am WEST/2:30pm IST/5am EST/2am PST

Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs. Visuals of your code update instantly and are cross-linked to your code to allow graphical

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Sigasi September Productivity Hacks Workshop

Sigasi September Productivity Hacks Workshop
by Admin on 08-15-2022 at 3:15 pm

Tuesday, September 13, 2022, at 8pm CEST/7pm WEST/2pm EST/11am PST/11:30pm IST

Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs. Visuals of your code update instantly and are cross-linked to your code to allow graphical

Read More

A Picture is worth a 1,000 words

A Picture is worth a 1,000 words
by Daniel Payne on 12-28-2017 at 7:00 am

Semiconductor IP re-use is a huge part of the productivity gains in SoC designs, so instead of starting from a clean slate most chip engineers are re-using cells, blocks, modules and even sub-systems from previous designs in order to meet their schedule and stay competitive in the market place. But what happens when you intend to… Read More


Dragging RTL Creation into the 21st Century

Dragging RTL Creation into the 21st Century
by Bernard Murphy on 07-29-2016 at 7:00 am

When I was at Atrenta, we always thought it would be great to do as-you-type RTL linting. It’s the natural use model for anyone used to writing text in virtually any modern application (especially on the Web, thanks to Google spell and grammar-checks). You may argue that you create your RTL in Vi or EMACS and you don’t need no stinking… Read More