A Brief History of RTL Design

RTL is an acronym for Register Transfer Level and refers to a level of hardware design abstraction using Registers and logic gates. Here’s an example schematic showing one DFF as a register, and one inverter as a logic gate.

Figure 1: RTL diagram of a DFF (D Flip Flop) and Inverter
The following Y-Chart was created by Gajski and Kuhn in 1983 and it shows that RTL is a design level between logic and algorithm.

Figure 2: Y-Chart, design abstraction levels

The advantage of using RTL over gate-level is that the higher level abstraction is more productive in defining and developing an electronic system using a technology-independent language.

RTL – Languages

Early Hardware Description Languages (HDL) that could model at the RTL level include:

• Late 1970’s HILO was created at Bradford University, commercialized by GenRad in the 1980’s
• ABEL in 1983 by Data-I/O

Verilog from Gateway Design Automation emerged in 1985 and was quickly adopted by the digital design community for designing and simulation of switches, gates and RTL levels. Gateway Design Automation was acquired by Cadence in 1989. The following Verilog code snippet describes the DFF and inverter from Figure 1:
always @(posedge clk) Q <= D;
assign D = ~Q;

Figure 3: Verilog code snippet for a DFF and Inverter

In the 1980’s the ASIC foundry business started offering Gate Arrays and Standard Cell design services, which could then be simulated with Verilog or foundry-specific simulators like TEGAS. By 1991 OVI (Open Verilog International) was formed which allowed other companies to create Verilog simulators.

Figure 4: Waveform Viewer for VCD (Verilog Change on Dump) files

The U.S. Department of Defense drove the specification for the VHDL language (VHSIC Hardware Description Language, VHSIC is Very High Speed Integrated Circuit) starting in 1981, specified by 1985, and become an IEEE standard in 1987.

Starting in the late 1980’s Verilog and VHDL became the two dominant HDL descriptions and continue to this day as SystemVerilog and VHDL 1076-2008, respectively.

Popular VHDL and Verilog simulators include:

• ModelSim from Mentor Graphics
• Incisive from Cadence Design
• VCS from Synopsys
• Riviera PRO from Aldec

RTL – Logic Synthesis

Logic synthesis is the automated process of transforming an HDL language like Verilog or VHDL into an optimized Gate-level description. The history of logic synthesis started in the 1960s:

• 1960s, D-algorithm applied to ATPG (Automatic Test Pattern Generation) used for boolean reasoning.
• 1978, formal equivalence checking introduced at IBM in the design of mainframe computers, SAS tool.
• 1979, IBM uses logic synthesis for Gate Array-based mainframe design. LSS tool, followed by BooleDozer.
• 1986, Synopsys founded and offers a logic remapper between Standard Cell libraries. Later adds RTL logic synthesis.

Figure 5: Logic Synthesis flow

Popular logic synthesis tools include:

• Design Compiler and Synplify from Synopsys
• RTL Compiler from Cadence
• Precision from Mentor Graphics
• RealTime Designer from Oasys
• XST from Xilinx
• Quartus from Altera

Summary

The RTL design methodology uses an HDL language for: design, simulation, verification, test and logic synthesis. The productivity benefits of designing at the RTL level has mostly replaced gate-level and transistor-level design for digital logic. Gate-level design is technology specific to a foundry, while RTL design is technology-independent which allows the designer to choose which foundry best fits their budget and requirements.

High Level Synthesis (HLS) is a higher level design methodology than RTL design and generally uses un-timed languages like SystemC, C or C++ for design entry and then synthesis down to the RTL or gate-levels.

Further Reading

EDA Company by Market Segment Wiki

EDA Mergers and Acquisitions Wiki

Design Automation Conference Wiki

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