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Low Frequency Noise Challenges IC Designs

Low Frequency Noise Challenges IC Designs
by Daniel Payne on 08-28-2016 at 7:00 am

AMS and RF IC designers have known for years that their circuits are sensitive to noise, because if you amplify noise on an input source to an amplifier circuit then your chip can start to produce wrong answers. Even digital SoC designers need to start taking notice because every SoC is filled with SRAM IP blocks, and at each shrinking… Read More


Bridging the Gap between Foundry and IC Design at #53DAC

Bridging the Gap between Foundry and IC Design at #53DAC
by Daniel Payne on 06-23-2016 at 12:00 pm

In our semiconductor ecosystem we often specialize the engineers and therefore EDA tools into separate silos like Foundry, front-end design, back-end design, tapeout, etc. What I discovered at #53DAC a few weeks ago was that some EDA companies actually bridge the gap between foundry engineers and IC designers with their tools.… Read More


The Emerging Importance of Parallel SPICE

The Emerging Importance of Parallel SPICE
by Tom Dillinger on 05-15-2016 at 7:00 am

SPICE simulation is the workhorse tool for custom circuit timing validation and electrical analysis. As the complexity of blocks and macros has increased in advanced process nodes — especially with post-layout extraction parasitic elements annotated to the circuit netlist — the model size and simulation throughput… Read More


Process Development, CAD and Circuit Design

Process Development, CAD and Circuit Design
by Daniel Payne on 04-29-2016 at 7:00 am

Working at Intel as a circuit designer I clearly remember how there were three distinct groups: Process Development, CAD and Circuit Design. Each of the groups sat in a different part of the building in Aloha Oregon, we had different job titles, different degrees, spoke with different acronyms and yet we all had to work together … Read More


The Importance of Transistor-Level Verification

The Importance of Transistor-Level Verification
by Students@olemiss.edu on 04-10-2016 at 7:00 am

Image RemovedAccording to the IEEE Std 1012-2012, verification is the acknowledgement that a product is in satisfactory condition by meeting a set of rigorous criteria. [3] Transistor-level verification involves the use of custom libraries and design models to achieve ultimate performance, low power, or layout density. … Read More


Webinar: A Tool for Process and Device Evaluation

Webinar: A Tool for Process and Device Evaluation
by Tom Simon on 03-24-2016 at 12:00 pm

Not only are foundries continuing to introduce processes at new advanced nodes, they are frequently updating or adding processes at existing nodes. There are many examples that illustrate this well. TSMC now has 16FF, 16FF+ and now 16FFC. They are also announcing 10nm and 7nm processes. In addition, they are going back to older… Read More