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SURGE 2018 Silvaco Update!

SURGE 2018 Silvaco Update!
by Daniel Nenni on 10-01-2018 at 7:00 am

The semiconductor industry has been very good to me over the past 35 years. I have had a front row seat to some of the most innovative and disruptive things like the fabless transformation and of course the Electronic Design Automation phenomenon, not to mention the end products that we as an industry have enabled. It is truly amazing… Read More


Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More


Affordable EDA Tools for IoT Designs, Guess which Vendor

Affordable EDA Tools for IoT Designs, Guess which Vendor
by Daniel Payne on 09-10-2018 at 12:00 pm

I just had to drive my car 7 miles from Tualatin, Oregon to visit with an EDA veteran who has played a lot of diverse roles in his career, including: IC Mask Designer, Layout Manager, Account Manager, Business Development, Director, Foundry Relations Director. His name is John Stabenow, with Mentor, a Siemens Business, and we met… Read More


Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that

Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that
by Daniel Payne on 08-24-2018 at 12:00 pm

There’s an old maxim that you can only improve what you measure, so quality experts have been talking about this concept for decades and our semiconductor industry has been the recipient of such practices to such an extent that we can now buy consumer products that include chips with over 5 billion transistors in them. You’ve… Read More


When it Comes to Process Migration, “Standard Cells” are Anything But

When it Comes to Process Migration, “Standard Cells” are Anything But
by Tom Simon on 08-22-2018 at 12:00 pm

Standard cell library developers are faced with a daunting task when it is time to create a library for a new process node. Porting an existing library can be a big help, but even then, manual modifications to 800 or more cells is still required. Each of those cells has many geometric elements are that affected by new design rules. All… Read More


Webinar: NetSpeed is about to change the way SOCs are designed

Webinar: NetSpeed is about to change the way SOCs are designed
by Tom Simon on 08-20-2018 at 12:00 pm

A large part of the effort in designing SOCs has shifted to the integration of their constituent IP blocks. Many IP blocks used in SOCs come as ready to use components and the real work has become making them work together. Network on Chip (NoC) has been a huge help in this task, handling the interconnections between blocks and planning… Read More


Netspeed and NSITEXE talk about automotive design trends at 55DAC

Netspeed and NSITEXE talk about automotive design trends at 55DAC
by Tom Simon on 08-02-2018 at 12:00 pm

DAC is where both sides of the design equation come together for discussion and learning. This is what makes attending DAC discussion panels so interesting; you are going to hear from providers of tools, methodologies and IP as well as those who need to use them to deliver working solutions. There are few places where the interplay… Read More


Optimization and Reliability for FinFET designs at #55DAC

Optimization and Reliability for FinFET designs at #55DAC
by Daniel Payne on 07-25-2018 at 7:00 am

TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what’s new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time… Read More


Maximize Bandwidth in your Massively Parallel AI SoCs?

Maximize Bandwidth in your Massively Parallel AI SoCs?
by Daniel Nenni on 07-20-2018 at 12:00 pm

Artificial Intelligence is one of the most talked about topics on the conference circuit this year and I don’t expect that to change anytime soon. AI is also one of the trending topics on SemiWiki with organic search bringing us a wealth of new viewers. You may also have noticed that AI is a hot topic for webinars like the one I am writing… Read More


Drop-In Security for IoT Edge Devices

Drop-In Security for IoT Edge Devices
by Bernard Murphy on 07-10-2018 at 7:00 am

You’re excited about the business potential for your cool new baby monitor, geo-fenced kid’s watch, home security system or whatever breakthrough app you want to build. You want to focus on the capabilities of the system, connecting it to the cloud and your marketing rollout plan. Then someone asks whether your system is architected… Read More