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When Design Gets Faster, the Bottleneck Moves Through the Physical Stack

When Design Gets Faster, the Bottleneck Moves Through the Physical Stack
by Moh Kolb on 09-07-2026 at 6:00 am

Desing fast Bott through physicalstack

AI can compress the path to tape-out. The next challenge is compressing physical realization.

Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.

AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More


Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry

Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry
by Daniel Nenni on 09-06-2026 at 10:00 am

Advanced Chip Packaging Comparison INtel TSMC Samsung

Advanced semiconductor packaging has become essential to improving computing performance as conventional transistor scaling grows more difficult and expensive. Instead of manufacturing an entire processor as one large monolithic die, chipmakers can divide it into smaller chiplets and combine logic, memory, input/output… Read More


Semicon West: Transforming Tomorrow One Chip at a Time

Semicon West: Transforming Tomorrow One Chip at a Time
by Daniel Nenni on 09-06-2026 at 6:00 am

Semicon West 2026 Transforming Tomorrow One Chip at a Time

SEMICON West 2026 arrives at a pivotal moment for the global chip industry. Scheduled for October 13–15 at San Francisco’s Moscone Center, the event returns to the Bay Area after its 2025 edition in Phoenix. Organized by SEMI under the theme “Transform Tomorrow,” it will bring together semiconductor manufacturers, equipment… Read More


The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response

The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response
by Kalar Rajendiran on 09-04-2026 at 6:00 am

2025 Design IP Sub Categories Market Share Pie Chart

While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More


HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory

HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory
by Admin on 09-03-2026 at 6:00 am

HBM’s Vertical Ascent

SK hynix’s Hot Chips 2026 presentation explains how High Bandwidth Memory (HBM) is evolving to meet the extraordinary memory requirements of artificial intelligence. Its central message is that future progress will depend not only on better DRAM circuits but also on advanced packaging, denser vertical integration, improved… Read More


Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First Generation

Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First Generation
by Daniel Nenni on 09-02-2026 at 10:00 am

Intel 18A P Extends Intel 18A with Significant Power and Performance Gains

Intel Foundry has a blog on LinkedIn that is worth a look. The blogs are by trusted Intel Foundry technical experts and are filled with content. I will cherry pick write a bit about them but be sure and subscribe to this, absolutely.

Intel 18A-P is not a new process node in the conventional sense. It is a performance-enhanced derivative… Read More


Intel’s 14A Is Winning the Race Against Defects

Intel’s 14A Is Winning the Race Against Defects
by Daniel Nenni on 08-31-2026 at 2:00 pm

Intel’s 14A Is Winning the Race Against Defects

Intel’s next-generation 14A manufacturing process is showing unusually strong early progress, with defect density falling faster than the company expected. The improvement gives Intel a technical boost as it attempts to restore confidence in its manufacturing operation, win foundry customers and demonstrate that years… Read More


TSMC’s Overseas Fabs Are Paying Off

TSMC’s Overseas Fabs Are Paying Off
by Daniel Nenni on 08-28-2026 at 6:00 am

TSMC's Overseas Fabs Are Paying Off

TSMC’s overseas fabrication strategy is beginning to deliver its intended return: not immediate cost parity with Taiwan, but manufacturable geographic redundancy, closer integration with major customers and access to subsidized capacity in strategically important markets. Arizona and Kumamoto are already producing … Read More


Crescent Island: Turning Memory Capacity into Agentic AI Throughput

Crescent Island: Turning Memory Capacity into Agentic AI Throughput
by Admin on 08-27-2026 at 2:00 pm

Intel Crecesent Island Hot Chips 2026

Intel’s Crescent Island is a discrete data-center GPU designed for agentic AI inference, where performance is constrained by more than matrix arithmetic. Multi-step agents impose latency through repeated model calls and tool interactions, consume large memory capacity for weights and long-context key-value caches, and… Read More


AI-designed Chip Points Toward a Faster Future for Custom Silicon

AI-designed Chip Points Toward a Faster Future for Custom Silicon
by Daniel Nenni on 08-27-2026 at 10:00 am

AI Designed Chip Why Redwood Matters

Architect Labs says it has created Redwood, an AI accelerator designed and verified almost entirely by artificial intelligence in less than two weeks. If independently validated and successfully translated from a programmable prototype into manufactured silicon, the project could represent a major change in how computer… Read More